Freescale Semiconductor MPC5200B ユーザーズマニュアル

11-36

Freescale Semiconductor

Ultra DMA mode 2 (UDMA2) requires that the ip bus clock speed is at least 66MHz.

 lists the redefined ultra DMA protocol signal lines. These lines provide new functions during the ultra DMA mode. At termination 

of an ultra DMA burst, the host negates DMACK and the lines revert to the definitions used for non-ultra DMA transfers.

Both the host and drive do a CRC function during an ultra DMA burst:

•

The host sends CRC data to the drive.

•

The drive does a CRC data comparison.

If the CRC comparison fails, the error register ERR bit is set. The drive always reports the first error that occurs.

The host asserts 

RESET

 for a minimum of 25µs after power has stabilized within system specified tolerance. A signal assertion less than 

20ns is not recognized by the drive.

The host should not do the following:

•

set the device control register bit SRST to 1 to enable the drive for software reset

•

issue a DEVICE RESET command while the status register BSY bit is set to 1.

Hardware reset is a board requirement, not an MPC5200B function unless GPIO is used.

The host sets the device control register bit SRST to 1. Any subsequent setting and clearing of the SRST bit must be at least 5µs apart.

 shows the Reset timing diagram. 

 gives timing characteristics.

DIOR

HDMARDY

Host DMA ready during Ultra DMA data in bursts

HSTROBE

Host data strobe during Ultra DMA data out bursts

IORDY

DDMARDY

Drive DMA ready during Ultra DMA data out bursts

DSTROBE

Drive data strobe during Ultra DMA data in bursts

DIOW

STOP

Host stop ultra DMA bursts