Freescale Semiconductor MPC5200B ユーザーズマニュアル
Host Control (HC) Operational Registers
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
12-19
12.4.5
Root Hub Partition—MBAR + 0x1048
This HC partition uses 5 32-bit registers. These registers are located at an offset from MBAR of 0x1048. Register addresses are relative to
this offset. Therefore, the actual register address is:
this offset. Therefore, the actual register address is:
MBAR + 0x1048 + register address
The following registers are available:
•
•
•
(0x1050)
•
•
All registers included in this partition are dedicated to the USB root hub, which is an integral part of the HC though still a functionally separate
entity. HCD emulates USBD access to the root hub via a register interface. HCD maintains many USB-defined hub features which are not
required to be supported in hardware. For example, the hub’s device, configuration, interface, and endpoint descriptors are maintained only
in the HCD and some class descriptor static fields. HCD also maintains and decodes the root hub device address as well as other trivial
operations better suited to software than hardware.
entity. HCD emulates USBD access to the root hub via a register interface. HCD maintains many USB-defined hub features which are not
required to be supported in hardware. For example, the hub’s device, configuration, interface, and endpoint descriptors are maintained only
in the HCD and some class descriptor static fields. HCD also maintains and decodes the root hub device address as well as other trivial
operations better suited to software than hardware.
The root hub register interface is otherwise developed to maintain similarity of bit organization and operation to typical hubs which are found
in the system. Each register is read and written as a 32-bit word. These registers are only written during initialization to correspond with the
system implementation.
in the system. Each register is read and written as a 32-bit word. These registers are only written during initialization to correspond with the
system implementation.
•
HcRhDescriptorA and HcRhDescriptorB registers should be implemented such that they are writeable regardless of the HC USB
state.
state.
•
HcRhStatus and HcRhPortStatus must be writeable during the USBOPERATIONAL state.
NOTE
IS denotes an implementation-specific reset value for that field.
12.4.5.1
USB HC Rh Descriptor A Register—MBAR + 0x1048
This register is the first of two registers describing the root hub characteristics. Reset values are implementation-specific. The HCD emulates
the following hub class descriptor fields:
the following hub class descriptor fields:
•
descriptor length (11)
•
descriptor type (TBD)
•
hub controller current (0)
All other fields are located in the HcRhDescriptorA and HcRhDescriptorB registers.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
LST
W
RESET:
0
0
0
0
1
1
0
0
0
1
0
1
0
0
0
0
Bits
Name
Description
0:19
—
Reserved
20:31
LST
LSThreshold—field contains a value which is compared to the FrameRemaining field prior to
initiating a low speed transaction. The transaction is started only if FrameRemaining is greater
than or equal to this field. HCD calculates this value with the consideration of transmission and
setup overhead.
initiating a low speed transaction. The transaction is started only if FrameRemaining is greater
than or equal to this field. HCD calculates this value with the consideration of transmission and
setup overhead.
Table 12-19. USB HC Rh Descriptor A Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
POTPGT
Reserved
W
RESET:
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0