Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
13-14
Freescale Semiconductor
BestComm DMA Registers—MBAR+0x1200
13.15.16 SDMA Initiator Priority 0 Register—MBAR + 0x123C
SDMA Initiator Priority 1 Register—MBAR + 0x123D
SDMA Initiator Priority 2 Register—MBAR + 0x123E
SDMA Initiator Priority 3 Register—MBAR + 0x123F
Table 13-16. SDMA Initiator Priority 0 Register
SDMA Initiator Priority 1 Register
SDMA Initiator Priority 2 Register
SDMA Initiator Priority 3 Register
SDMA Initiator Priority 2 Register
SDMA Initiator Priority 3 Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
IPR0
Hold
Reserved
Prior [2:0]
IPR1
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
IPR2
IPR3
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description
Each of the thirty-two initiators has an associated priority level. Only one register is shown. All bits are set to ‘0 at reset.
0
IPR0 Hold
Hold - Keep current priority of initiator
0 = Allow higher priority initiator to block current initiator
1 = Hold current initiator priority level
This bit can be set or cleared by the programmer at any time. This bit allows the current
initiator to hold priority until the initiator has negated or the task has finished. When this bit
is cleared, an initiator with a higher priority will block the current initiator and force
arbitration. At system reset, this bit is cleared.
initiator to hold priority until the initiator has negated or the task has finished. When this bit
is cleared, an initiator with a higher priority will block the current initiator and force
arbitration. At system reset, this bit is cleared.
1:4
—
Reserved
5:7
Prior[2:0]
InitPrior[2:0] - Initiator/Task priority level.
These bits can be set by the programmer at any time. These bits control the priority of the
requestor/task which will be serviced next depending on the setting of the T/I bit in the
PtdControl register.
requestor/task which will be serviced next depending on the setting of the T/I bit in the
PtdControl register.
The highest priority is level 7. The lower priority is level 0.. If more than one initiator/task
contains the same priority then the order of the task within the Task table (task 7 highest
to task 0 lowest) will set the priority.
contains the same priority then the order of the task within the Task table (task 7 highest
to task 0 lowest) will set the priority.
8:15
IPR1
Initiator Priority register for initiator 1 (or Task1 if PtdControl[16]=1).
Same bit layout as IPR0
16:23
IPR2
Initiator Priority register for initiator 2.(or Task2 if PtdControl[16]=1)
Same bit layout as IPR0
24:31
IPR3
Initiator Priority register for initiator 3.(or Task3 if PtdControl[16]=1)
Same bit layout as IPR0