Freescale Semiconductor MPC5200B ユーザーズマニュアル
Overview
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
2-1
Chapter 2
Signal Descriptions
Signal Descriptions
2.1
Overview
The MPC5200B contains a e300 core, an internal DMA engine, BestComm, multiple functional blocks and associated I/O ports. There are
two external data/address bus structures, the LocalPlus bus and SDRAM bus. A block diagram of the MPC5200B structure is shown in Figure
1-1.
two external data/address bus structures, the LocalPlus bus and SDRAM bus. A block diagram of the MPC5200B structure is shown in Figure
1-1.
In general, the LocalPlus bus connects to external SRAM, FLASH, peripheral devices, etc. The LocalPlus bus is capable of executing standard
memory cycles, PCI cycles and ATA cycles. In addition to the data and address bus pins on the LocalPlus bus, there are pins specifically
dedicated to ATA transactions, PCI transactions and standard memory transactions. When the MPC5200B is released from reset, Chip Select
0 is the only active chip select. Program execution must always start from the “boot device” on the LocalPlus bus. There are 8 chip select
signals associated with the LocalPlus bus. It’s possible to execute from every CS. Also every CS can address “data space”.
memory cycles, PCI cycles and ATA cycles. In addition to the data and address bus pins on the LocalPlus bus, there are pins specifically
dedicated to ATA transactions, PCI transactions and standard memory transactions. When the MPC5200B is released from reset, Chip Select
0 is the only active chip select. Program execution must always start from the “boot device” on the LocalPlus bus. There are 8 chip select
signals associated with the LocalPlus bus. It’s possible to execute from every CS. Also every CS can address “data space”.
The SDRAM bus interfaces to Synchronous DRAM. Both Single Data Rate and Double Data Rate DRAMs are supported. Executable
programs are generally loaded into memory residing on the SDRAM bus. The SDRAM bus has a 32-bit wide data/address bus structure and
is capable of burst accesses. It is possible to execute program code over the LocalPlus bus. However, the data transfer rate on the SDRAM
bus is many times faster than LocalPlus.
programs are generally loaded into memory residing on the SDRAM bus. The SDRAM bus has a 32-bit wide data/address bus structure and
is capable of burst accesses. It is possible to execute program code over the LocalPlus bus. However, the data transfer rate on the SDRAM
bus is many times faster than LocalPlus.
There are 16 peripheral functional blocks on the MPC5200B. These are General Purpose I/O, I2C, TIMER, PSC1, PSC2, PSC3, PSC4, PSC5,
PSC6, Ethernet, USB, MSCAN, SPI and J1850. Each of these functional blocks are routed to one or more I/O ports through a system of
multiplexers. A functional block can only be routed to one I/O port at a time and in many cases, several functional blocks can be routed to the
same I/O port.
PSC6, Ethernet, USB, MSCAN, SPI and J1850. Each of these functional blocks are routed to one or more I/O ports through a system of
multiplexers. A functional block can only be routed to one I/O port at a time and in many cases, several functional blocks can be routed to the
same I/O port.
The I/O ports are Dedicated GPIO Group, I
2
C Group, Timer Group, PSC1 Group, PSC2 Group, PSC3 Group, PSC6 Group, Ethernet Group,
and the USB Group.
Figures 2-2 through 2-10 present detailed on the multiplexing options for each I/O port.
MPC5200B is packaged in a 272-pin Plastic Ball Gate Array (PBGA). Package ball locations are shown in
. See Appendix D, for
case diagram.