Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
14-6
Freescale Semiconductor
FEC Memory Map and Registers
14.3.1.2.1
MII Management Register Set
The MII management register set located in the PHY may consist of a basic register set and an extended register set as defined in
14.4
FEC Memory Map and Registers
The FEC device is programmed by a combination of control/status registers (CSRs) and BestComm task loops. Since the FEC software model
is BestComm-based, there is no similarity with existing CPM-based products’ coding.
is BestComm-based, there is no similarity with existing CPM-based products’ coding.
The CSRs are used for mode control, interrupts and extraction of status information. BestComm tasks are used to pass data buffers and related
buffer or frame information between the hardware and software.
buffer or frame information between the hardware and software.
All access via microprocessor to and from the registers must be 32-bit accesses. There is no support for accesses other than 32-bit. All access
via BestComm to and from the registers may be byte, word or longword (32-bit) accesses. Top Level Module Memory Map
via BestComm to and from the registers may be byte, word or longword (32-bit) accesses. Top Level Module Memory Map
The FEC implementation requires a 2KByte memory map space. This is divided into two sections of 512 Bytes and an additional 1KBytes
of reserved space. The first 512 Bytes is used for Control and Status Registers. The second contains event/statistic counters held in the MIB
block.
of reserved space. The first 512 Bytes is used for Control and Status Registers. The second contains event/statistic counters held in the MIB
block.
defines the top level memory map.
Table 14-4. MMI Format Definitions
Name
Description
<preamble>
Optional—consists of a sequence of 32 continuous logic 1s.
<st>
Start of frame—indicated by a <01> pattern.
<op>
Operation code:
Read instruction is <10>
Write instruction is <01>
<phyad>
A 5-bit field that lists up to 32 PHYs be addressed. The first address bit transmitted is the
msb of the address.
msb of the address.
<regad>
A 5-bit field that lets 32 registers be addressed within each PHY. The first register bit
transmitted is the msb of the address.
transmitted is the msb of the address.
<ta>
A 2-bit field that provides spacing between the register address field and the data field to
avoid contention on the MDIO signal during a read operation.
avoid contention on the MDIO signal during a read operation.
<data>
Data field is 16 bits wide. Data bit 15 is first bit transmitted and received.
<idle>
During idle condition, MDIO is in the high impedance state.
Table 14-5. MII Management Register Set
Register Address
Register Name
Basic/Extended
0
Control
B
1
Status
B
2:3
PHY Identifier
E
4
Auto-Negotiation Advertisement
E
5
AN Link Partner Ability
E
6
AN Expansion
E
7
AN Next Page Transmit
E
8:15
Reserved
E
16:31
Vendor Specific
E