Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
14-14
Freescale Semiconductor
FEC Registers—MBAR + 0x3000
14.5.3
FEC Interrupt Enable Register—MBAR + 0x3008
The IMASK register provides control over the interrupt events allowed to generate an interrupt. All implemented bits in this CSR are R/W.
This register is cleared by a hardware reset. If corresponding bits in both the IEVENT and IMASK registers are set, the interrupt is signalled
to the CPU. The interrupt signal remains asserted until 1 is written to the IEVENT bit (write 1 to clear) or a 0 is written to the IMASK bit.
This register is cleared by a hardware reset. If corresponding bits in both the IEVENT and IMASK registers are set, the interrupt is signalled
to the CPU. The interrupt signal remains asserted until 1 is written to the IEVENT bit (write 1 to clear) or a 0 is written to the IMASK bit.
14.5.4
FEC Rx Descriptor Active Register—MBAR + 0x3010
The FEC descriptor active register is a command register which should be written by the user to indicate that the receive descriptor ring has
been updated (empty receive buffers have been produced by the driver with the E bit set).
been updated (empty receive buffers have been produced by the driver with the E bit set).
Whenever the register is written the R_DES_ACTIVE bit is set. This is independent of the data actually written by the user. When set, the
FEC will poll the receive descriptor ring and process receive frames (provided ETHER_EN is also set). Once the FEC polls a receive
descriptor whose ownership bit is not set, then the FEC will clear the R_DES_ACTIVE bit and cease receive descriptor ring polling until the
user sets the bit again, signifying additional descriptors have been placed into the receive descriptor ring.
FEC will poll the receive descriptor ring and process receive frames (provided ETHER_EN is also set). Once the FEC polls a receive
descriptor whose ownership bit is not set, then the FEC will clear the R_DES_ACTIVE bit and cease receive descriptor ring polling until the
user sets the bit again, signifying additional descriptors have been placed into the receive descriptor ring.
Table 14-11. FEC Interrupt Enable Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
HBEEN
BREN
BTEN
G
R
AEN
TF
IEN
Reserved
MIIEN
Rsvd
LCEN
CRLEN
X
F
UNEN
XFER
REN
R
F
ERREN
Rsvd
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0
HBEEN
Heartbeat Error Interrupt Enable
1
BREN
Babbling Receiver Interrupt Enable
2
BTEN
Babbling Transmitter Interrupt Enable
3
GRAEN
Graceful Stop Interrupt Enable
4
TFIEN
Transmit Frame Interrupt Enable
5
—
Reserved
6
—
Reserved
7
—
Reserved
8
MIIEN
MII Interrupt Enable
9
—
Reserved
10
LCEN
Late Collision Enable
11
CRLEN
Late Collision Enable
12
XFUNEN
Transmit FIFO Underrun Enable
13
XFERREN
Transmit FIFO Error Enable
14
RFERREN
Receive FIFO Error Enable
15:31
—
Reserved