Freescale Semiconductor MPC5200B ユーザーズマニュアル
Initialization Sequence
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
14-43
Pause frame detection is performed by the receiver and microcontroller modules. The microcontroller runs an address recognition subroutine
to detect the specified pause frame destination address, while the receiver detects the type and opcode pause frame fields. On detection of a
pause frame, graceful transmit stop is asserted by the FEC internally. When transmission has paused, the GRA (Graceful Stop complete)
interrupt is asserted and the pause timer begins to increment. Note that the pause timer makes use of the transmit backoff timer hardware which
is used for tracking the appropriate collision backoff time in half-duplex mode. The pause timer increments once every slot time until
PAUSE_DURATION slot times have expired. On PAUSE_DURATION expiration, graceful transmit stop is deasserted allowing MAC data
frame transmission to resume. Note that the receive flow control pause (X_CNTRL.RFC_PAUSE) status bit is asserted while the transmitter
is paused due to reception of a pause frame.
to detect the specified pause frame destination address, while the receiver detects the type and opcode pause frame fields. On detection of a
pause frame, graceful transmit stop is asserted by the FEC internally. When transmission has paused, the GRA (Graceful Stop complete)
interrupt is asserted and the pause timer begins to increment. Note that the pause timer makes use of the transmit backoff timer hardware which
is used for tracking the appropriate collision backoff time in half-duplex mode. The pause timer increments once every slot time until
PAUSE_DURATION slot times have expired. On PAUSE_DURATION expiration, graceful transmit stop is deasserted allowing MAC data
frame transmission to resume. Note that the receive flow control pause (X_CNTRL.RFC_PAUSE) status bit is asserted while the transmitter
is paused due to reception of a pause frame.
To transmit a pause frame the FEC must operate in full-duplex mode and the user must assert flow control pause (X_CNTRL.TFC_PAUSE).
On assertion of transmit flow control pause (X_CNTRL.TFC_PAUSE) the transmitter asserts graceful transmit stop internally. When the
transmission of data frames stops the GRA (Graceful Stop complete) interrupt asserts. Following GRA assertion the Pause frame is
transmitted. On completion of pause frame transmission flow control pause (X_CNTRL.TFC_PAUSE) and graceful transmit stop are
deasserted internally.
On assertion of transmit flow control pause (X_CNTRL.TFC_PAUSE) the transmitter asserts graceful transmit stop internally. When the
transmission of data frames stops the GRA (Graceful Stop complete) interrupt asserts. Following GRA assertion the Pause frame is
transmitted. On completion of pause frame transmission flow control pause (X_CNTRL.TFC_PAUSE) and graceful transmit stop are
deasserted internally.
During pause frame transmission the transmit hardware places data into the transmit data stream from the registers shown in the table below.
The user must specify the desired pause duration in the OP_PAUSE register.
Note that when the transmitter is paused due to receiver/microcontroller pause frame detection, transmit flow control pause
(X_CNTRL.TFC_PAUSE) still may be asserted and will cause the transmission of a single pause frame. In this case the GRA interrupt will
not be asserted.
(X_CNTRL.TFC_PAUSE) still may be asserted and will cause the transmission of a single pause frame. In this case the GRA interrupt will
not be asserted.
14.9.8
Inter-Packet Gap Time
The minimum inter packet gap time for back-to-back transmission is 96 bit times. After completing a transmission or after the backoff
algorithm completes the transmitter waits for carrier sense to be negated before starting its 96 bit time IPG counter. Frame transmission may
begin 96 bit times after carrier sense is negated if it stays negated for at least 60 bit times. If carrier sense asserts during the last 36 bit times
it will be ignored and a collision will occur.
algorithm completes the transmitter waits for carrier sense to be negated before starting its 96 bit time IPG counter. Frame transmission may
begin 96 bit times after carrier sense is negated if it stays negated for at least 60 bit times. If carrier sense asserts during the last 36 bit times
it will be ignored and a collision will occur.
The receiver receives back-to-back frames with a minimum spacing of at least 28 bit times. If an inter-packet gap between receive frames is
less than 28 bit times the following frame may be discarded by the receiver.
less than 28 bit times the following frame may be discarded by the receiver.
14.9.9
Collision Handling
If a collision occurs during frame transmission the Ethernet controller will continue the transmission for at least 32 bit times, transmitting a
JAM pattern consisting of 32 one’s. If the collision occurs during the preamble sequence the JAM pattern will be sent after the end of the
preamble sequence.
JAM pattern consisting of 32 one’s. If the collision occurs during the preamble sequence the JAM pattern will be sent after the end of the
preamble sequence.
Table 14-46. PAUSE Frame Field Specification
48-bit destination address
0180_c200_0001 or Physical ADDRESS
48-bit Source Address
any
16-bit type
8808
16-bit opcode
0001
16-bit PAUSE duration
0000 to ffff
Table 14-47. Transmit Pause Frame Registers
PAUSE FRame fields
FEC register
Register Contents
48-bit destination address
{FDXFC_DA1[0:31], FDXFC_DA2[0:15]}
0180_c200_0001
48-bit Source Address
{PADDR1[0:31], PADDR2[0:15]}
physical address
16-bit type
PADDR2[16:31]
8808
16-bit opcode
OP_PAUSE[0:15]
0001
16-bit PAUSE duration
OP_PAUSE[16:31]
0000 to ffff