Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
15-18
Freescale Semiconductor
PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
15.2.9
Auxiliary Control Register (0x10)
—
ACR
The write-only ACR register controls Tx/Rx handshaking.
Bit
Name
Description
0
SYNC
Codec—Sync detected.
0 = Has not detected sync.
1 = Detected sync (Frame = 1 in Codec Modes or Sync = 1 in AC97 mode)
other Modes—Reserved
1
—
Reserved
2
D_DCD
Delta DCD.
0 = No change-of-state has occurred since the last time the CPU read the
. A read of
the IPCR also clears the IPCR D_DCD bit.
1 = A change of state, lasting more than a certain time (1/16 or 1bit duration determined by
the CSR,
the CSR,
and
) has occurred at DCD input. When this bit is set, the ACR can be
programmed to generate an interrupt to the processor.
3
D_CTS
Delta CTS.
0 = No change-of-state has occurred since the last time the CPU read the
. A read of
also clears the IPCR D_CTS bit.
1 = A change of state, lasting a certain time has occurred at CTS input. When this bit is set,
the
the
can be programmed to generate an interrupt to the processor.
After the enable of the PSC the CPU must read this bit to make sure, that this bit is cleared at
the beginning of the transmission.
the beginning of the transmission.
4:5
—
Reserved
6
DCD
Current state of DCD port. This input is double latched.
0 = The current state of the DCD input port is low.
1 = The current state of the DCD input port is high.
7
CTS
Current state of CTS port. This input is double latched.
0 = The current state of the CTS input port is low.
1 = The current state of the CTS input port is high.
Table 15-25. PSC 1 Auxiliary Control Register (0x10) for all Modes
msb 0
1
2
3
4
5
6
7 lsb
R
Reserved
W
Reserved
IEC1
IEC0
RESET:
0
0
0
0
0
0
0
0
Bit
Name
Description
0:5
—
Reserved