Freescale Semiconductor MPC5200B ユーザーズマニュアル
PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
15-41
15.2.37
Rx FIFO Last Write Frame PTR (0x7C)—RFLWFPTR
15.2.38
Tx FIFO Data (0x80)—TFDATA
Read - write register to access the internal TX FIFO Data register. Write to this register write data to the transmit FIFO. Additional the register
provide the possibility to read data back from the TX FIFO for debug issues. For more informations about the data format see
provide the possibility to read data back from the TX FIFO for debug issues. For more informations about the data format see
15.2.39
Tx FIFO Status (0x84)—TFSTAT
For additional informations about the FIFO related status bits see
NOTE
To make sure that the PSC never lost the data in the FIFO, the PSC controller avoid writing to a full
FIFO or reading from an empty FIFO. Therefore the status bits in the FIFO STAT register never
reports an ERROR, UF or OF state. The
FIFO or reading from an empty FIFO. Therefore the status bits in the FIFO STAT register never
reports an ERROR, UF or OF state. The
register reports these errors.
Table 15-65. Rx FIFO Last Write Frame PTR (0x7C)
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 lsb
R
Reserved
LFP
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description
0:3
—
Reserved
4:15
LFP
Last Frame Pointer. Not applicable to PSC FIFOs, since the PSCs do not recognize frame
formats in the serial data stream.
formats in the serial data stream.
Table 15-66. Tx FIFO STAT (0x84)
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 lsb
R
Reserved
F
rame[
3
]
F
rame[
2
]
F
rame[
1
]
F
rame[
0
]
Rese
rved
Error
UF
OF
FR
FULL
ALARM
EMPTY
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description
0:3
—
Reserved
4:7
Frame[3:0]
Frame indicator. Not applicable to PSC FIFOs, since the PSCs do not recognize frame
formats in the serial data stream.
formats in the serial data stream.
8
—
Reserved
9
Error
FIFO error. A FIFO error has occurred due to either underflow, overflow, or read or write
pointer out of bounds.This bit is cleared by writing 1 to it.
pointer out of bounds.This bit is cleared by writing 1 to it.
10
UF
Underflow. The read pointer has surpassed the write pointer due to the FIFO having been
read when it contained no data. This bit is cleared by writing 1 to it.
read when it contained no data. This bit is cleared by writing 1 to it.
11
OF
Overflow. The write pointer has surpassed the read pointer due to the FIFO having been
written when it was already completely full of data. This bit is cleared by writing 1 to it.
written when it was already completely full of data. This bit is cleared by writing 1 to it.
12
FR
Frame ready. Not applicable to PSC FIFOs, since the PSCs do not recognize frame formats
in the serial data stream.
in the serial data stream.
13
FULL
Full. The FIFO is completely full of data.