Freescale Semiconductor MPC5200B ユーザーズマニュアル

Freescale Semiconductor

15-65

the slot request for the specified slots was active (slot request bit was zero in the previous frame). If the AC97 Codec set a slot request to one, 
then the transmitter will send a complete empty frame because the transmitter is not able to send a port of the required slots without changing 
the order of the data in the FIFO.

If the software will send a command to the AC97 codec the “Control Register Index” and the “Control Register Write Data“ values must be 
written to the 

 register. A write access to any word of this register will trigger the transmitter to send out the register value, 

synchronous the 

[CMD_SEND] bit was set. The transmitter generate a slot0 tag which mark slot1 and slot2 as valid slot. If the receiver 

was able to send out the command data, the 

[CMD_SEND] bit will be cleared.

If the receiver detect a valid data in time slot2, then the 

[DATA_VALID] bit was set by the receiver. The software can read the received 

data from the 

register, synchronous the read access to this register will clear the 

[DATA_VALID] bit. If the receive detect an 

additional command data before the previous data was read out, the 

[DATA_OVR] bit was also set to one. The previous received command 

data word goes lost. A read access tot the 

AC97Data 

register will clear the 

[DATA_VALID] and 

[DATA_OVR] register. 

shows an example how to configure the AC97 controller. In this example the AC97 controller will only send time slot 3 and slot4 data and 
will expect data for time slot9,10,11 and 12 on the receive site. For this purpose the software must write 2 data words to the TxFIFO for one 
complete AC97 frame and must read 4 data words from the RxFIFO per frame.

The PSC support 3 different IrDA modes. These modes are described in the follows sections.

The SIR mode is one of the supported IrDA modes. This section will give some more informations about this mode. The imported register to 
configure the PSC6 (only this PSC support the IrDA modes) for SIR mode are:

•

 register - select the SIR mode

•

, 

 register - select the Baud rate

•

 register - select the Receiver interrupt mode

•

 register - Channel Mode

•

 register - select the pulse width

•

IRSDR register - select the counter for pulse width

•

TFALARM

 - select the FIFO “Alarm” level 

•

 register - enable or disable receiver and transmitter

•

Port_config - select the right Pin-Muxing, see 

The 

shows the interface signal definition. This definition is equal for all IrDA modes. The 

 shows the PSC in SIR 

mode. The simplified block diagram describe the clock distribution.

0x0A

Disable the Tx and Rx part for configuration if the PSC was enabled by the work 
before.

0x03010000

Select the enhanced AC97 mode

AC97Slots

0x0300000F

define the expected receive and transmit slots

0x0XXX

Choose Rx FIFO “almost full” threshold level.

TFALARM

0x0XXX

Choose Tx FIFO “almost empty” threshold level.

0xXXXX

select the desired interrupt

Port_Config

0x00000020

Select the Pin-Muxing for AC97 mode PSC2, see 

0x05

Enable Tx and Rx