Freescale Semiconductor MPC5200B ユーザーズマニュアル
PSC Operation Modes
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
15-69
The STA represents the start of the frame and the STO represents the end of the frame. Both of STA and STO are defined as 01111110 in
binary format. Like the UART mode, the MIR mode sends the lsb first.The FCS is a 16 bit CRC defined as
binary format. Like the UART mode, the MIR mode sends the lsb first.The FCS is a 16 bit CRC defined as
NOTE
The MIR module doesn’t support the CRC generation. If the transfer require a CRC Field use the
CRC generation from the BestComm module. See also
CRC generation from the BestComm module. See also
15.3.4.2.3
Serial Interaction Pulse (SIP)
The MIR and FIR system must emit SIP (Serial Interaction Pulse) at least once per 500ms while the connection lasts, in order to inform slower
systems (SIR) not to interfere the link. If the SIPEN bit in
systems (SIR) not to interfere the link. If the SIPEN bit in
is high, the transmitter automatically append one SIP after every frame. SIP
can be also sent by writing 1 to SIPREQ bit in
. If SIPREQ is high and the transmitter is in idle state, one SIP is sent and SIPREQ bit
is automatically cleared. The SIP is defined as:
Figure 15-20. Serial Interaction Pulse (SIP)
15.3.4.2.4
Configuration Sequence Example for MIR Mode
This list includes the MIR mode related registers only, not the other configure values like interrupt and FIFO configurations. PSC module
registers can be accessed by word or byte operations. The
registers can be accessed by word or byte operations. The
shows the configuration sequences for follow example:
•
PSC6 in IrDA MIR mode
•
MIR mode: 1.152 Mbps, SIP pulse after every transfer
•
Mclk frequency: 27.78 MHz
•
IrdaClk: 9.26 MHz
NOTE
Please choose first the desired mode (MIR mode) than configure the port (write to port_config
register). This sequence will avoid pulses on the TX line during port configuration. This is very
important for all IrDA (SIR, MIR, and FIR) modes
register). This sequence will avoid pulses on the TX line during port configuration. This is very
important for all IrDA (SIR, MIR, and FIR) modes
Table 15-92. Configuration Sequence Example for MIR Mode
Register
Value
Setting
0x0A
Disable the Tx and Rx part for configuration if the PSC was
enabled by the work before.
enabled by the work before.
0x05800000
Select the MIR mode, use internal clock
cdm_irda_bitclk_config
0x80012
set Mclk to 27.78 Mhz, see
cdm_clock_enable_register
0x00000010
enable Mclk, see
0x0002
set IrdaClk to 9.26 MHz
0x02
enable SIP
0x07
set Baud rate to 1.152 Mbps
0x0XXX
Choose Rx FIFO “almost full” threshold level.
TFALARM
0x0XXX
Choose Tx FIFO “almost empty” threshold level.
CRC x
( )
x
16
x
12
x
5
1
+
+
+
=
1.6
µs
8.7
µs