Freescale Semiconductor MPC5200B ユーザーズマニュアル

Freescale Semiconductor

16-1

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The purpose of the XLB Arbiter is to manage bus requests from the XLB masters (USB, PCI, BestComm, and e300 core), and determine 
which master should be granted the bus at any one time. The arbiter employs both master prioritization and a fair-share LRU 
(least-recently-used) algorithm to reduce access latency and starvation across all masters. 

The XLB Arbiter consists of five functional blocks as shown below.

The prioritization block signals that a master is requesting the bus and which master has priority. 

Priority is determined first by using the master priority level assigned by either the hardware-wired internal signals, or software-programmable 
Master N Priority bits in the Arbiter Master N Priority Register depending on the Master Priority Enable bit for each master. Masters at the 
same level of priority will be further sorted by a least recently used algorithm (LRU). Once a requesting master is identified as having priority 
and is granted the bus, that master will be continue to be granted the bus if:

1.

It is requesting the bus. The request must occur immediately after the required one clock de-assertion after a qualified bus grant, and

2.

It is the highest priority device, and

3.

There is no address retry assertion.