Freescale Semiconductor MPC5200B ユーザーズマニュアル

Freescale Semiconductor

17-1

The following sections are contained in this document:

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The Serial Peripheral Interface (SPI) allows full-duplex, synchronous, serial communication between the MPC5200B and peripheral devices. 
Software can poll the SPI status flags or the SPI operation can be interrupt driven.

Figure 17-1

 shows the SPI block diagram.

The SPI has the following features:

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Master mode and slave mode

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Bi-directional mode

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Slave-select output

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Mode fault error flag with CPU interrupt capability

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Double-buffered data register

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Serial clock with programmable polarity and phase

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Control of SPI operation during wait mode

8-BIT Shift Register

Read Data Buffer

Shift Control Logic

SPI Status Register

SPI Data Register

SPIF

WCOL

MODF

SPI Interrupt

SPR2

SPR1

SPR0

Requ

est

SPIE

SPE

MSTR

CPO

L

CPH

A

LS

B

F

E

LSBFE

SPISWAI

SPC0

SWOM

SSOE

SPE

Clock

MSTR

SWOM

S

PPR2

SPPR1

SPPR0

MISO

MOSI

SCK

SS

DIVIDER

2

4

8 16

32 64 128 256

SELECT

SPI Baud Rate Register

Clock

Logic

SPI Control Register 2

SPI Control Register 1

S
M

M

S

M

S