Freescale Semiconductor MPC5200B ユーザーズマニュアル
Functional Description
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
20-17
Messages transmitted by the BDLC module onto the J1850 bus must contain at least one data byte, and therefore can be as short as
one data byte and one CRC byte. Each data byte in the message is 8 bits in length, transmitted MSB to LSB.
one data byte and one CRC byte. Each data byte in the message is 8 bits in length, transmitted MSB to LSB.
•
CRC - Cyclical Redundancy Check Byte
This byte is used by the receiver(s) of each message to determine if any errors have occurred during the transmission of the message.
The BDLC calculates the CRC byte and appends it onto any messages transmitted onto the J1850 bus, and also performs CRC
detection on any messages it receives from the J1850 bus.
The BDLC calculates the CRC byte and appends it onto any messages transmitted onto the J1850 bus, and also performs CRC
detection on any messages it receives from the J1850 bus.
CRC generation uses the divisor polynomial X
8
+X
4
+X
3
+X
2
+1. The remainder polynomial is initially set to all ones, and then each
byte in the message after the SOF symbol is serially processed through the CRC generation circuitry. The one’s complement of the
remainder then becomes the 8-bit CRC byte, which is appended to the message after the data bytes, in MSB to LSB order.
remainder then becomes the 8-bit CRC byte, which is appended to the message after the data bytes, in MSB to LSB order.
When receiving a message, the BDLC uses the same divisor polynomial. All data bytes, excluding the SOF and EOD symbols, but
including the CRC byte, are used to check the CRC. If the message is error free, the remainder polynomial will equal X
including the CRC byte, are used to check the CRC. If the message is error free, the remainder polynomial will equal X
7
+X
6
+X
2
($C4), regardless of the data contained in the message. If the calculated CRC does not equal $C4, the BDLC will recognize this as
a CRC error and set the CRC error flag in the BDLC State Vector Register.
a CRC error and set the CRC error flag in the BDLC State Vector Register.
•
EOD - End of Data Symbol
The EOD symbol is a long passive period on the J1850 bus used to signify to any recipients of a message that the transmission by
the originator has completed. No flag is set upon reception of the EOD symbol.
the originator has completed. No flag is set upon reception of the EOD symbol.
•
IFR - In Frame Response Bytes
The IFR section of the J1850 message format is optional. Users desiring further definition of in-frame response should review the
“SAE J1850 Class B Data Communications Network Interface” specification.
“SAE J1850 Class B Data Communications Network Interface” specification.
•
EOF - End of Frame Symbol
This symbol is a passive period on the J1850 bus, longer than an EOD symbol, which signifies the end of a message. Since an EOF
symbol is longer than an EOD symbol, if no response is transmitted after an EOD symbol, it becomes an EOF, and the message is
assumed to be completed. The EOF flag is set upon receiving the EOF symbol.
symbol is longer than an EOD symbol, if no response is transmitted after an EOD symbol, it becomes an EOF, and the message is
assumed to be completed. The EOF flag is set upon receiving the EOF symbol.
•
IFS - Inter-Frame Separation Symbol
The IFS symbol is a passive period on the J1850 bus which allows proper synchronization between nodes during continuous
message transmission. The IFS symbol is transmitted by a node following the completion of the EOF period.
message transmission. The IFS symbol is transmitted by a node following the completion of the EOF period.
When the last byte of a message has been transmitted onto the J1850 bus, and the EOF symbol time has expired, all nodes must then
wait for the IFS symbol time to expire before transmitting an SOF, marking the beginning of another message.
wait for the IFS symbol time to expire before transmitting an SOF, marking the beginning of another message.
However, if the BDLC module is waiting for the IFS period to expire before beginning a transmission and a rising edge is detected
before the IFS time has expired, it will internally synchronize to that edge.
before the IFS time has expired, it will internally synchronize to that edge.
A rising edge may occur during the IFS period because of varying clock tolerances and loading of the J1850 bus, causing different
nodes to observe the completion of the IFS period at different times. Receivers must synchronize to any SOF occurring during an
IFS period to allow for individual clock tolerances.
nodes to observe the completion of the IFS period at different times. Receivers must synchronize to any SOF occurring during an
IFS period to allow for individual clock tolerances.
•
Break
If the BDLC module is transmitting at the time a BREAK is detected, it treats the BREAK as if a transmission error had occurred,
and halts transmission.The BDLC module can transmit a BREAK symbol. If while receiving a message the BDLC module detects
a BREAK symbol, it treats the BREAK as a reception error and sets the invalid symbol flag. If while receiving a message in 4X
mode, the BDLC module detects a BREAK symbol, it treats the BREAK as a reception error, sets BDLC State Vector Register
register to $1C, and exits 4X mode.The 4XE bit in BDLC Control Register 2 is automatically cleared upon reception of the BREAK
symbol.
and halts transmission.The BDLC module can transmit a BREAK symbol. If while receiving a message the BDLC module detects
a BREAK symbol, it treats the BREAK as a reception error and sets the invalid symbol flag. If while receiving a message in 4X
mode, the BDLC module detects a BREAK symbol, it treats the BREAK as a reception error, sets BDLC State Vector Register
register to $1C, and exits 4X mode.The 4XE bit in BDLC Control Register 2 is automatically cleared upon reception of the BREAK
symbol.
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Idle Bus
An idle condition exists on the bus during any passive period after expiration of the IFS period. Any node sensing an idle bus
condition can begin transmission immediately.
condition can begin transmission immediately.
20.8.1.2
J1850 VPW Symbols
Variable Pulse Width modulation (VPW) is an encoding technique in which each bit is defined by the time between successive transitions,
and by the level of the bus between transitions, active or passive. Active and passive bits are used alternately. This encoding technique is used
to reduced the number of bus transitions for a given bit rate. See
and by the level of the bus between transitions, active or passive. Active and passive bits are used alternately. This encoding technique is used
to reduced the number of bus transitions for a given bit rate. See
The symbol values shown below are nominal values. Refer to the electrical specification for a more complete description of symbol values.
Each logic one or logic zero contains a single transition, and can be at either the active or passive level and one of two lengths, either 64
Each logic one or logic zero contains a single transition, and can be at either the active or passive level and one of two lengths, either 64
µs or
128
µs (T
NOM
at 10.4kbps baud rate), depending upon the encoding of the previous bit. The SOF, EOD, EOF and IFS symbols will always be
encoded at an assigned level and length. See