Freescale Semiconductor MPC5200B ユーザーズマニュアル

Freescale Semiconductor

20-31

Due to the byte-level architecture of the BDLC module, the 12-byte limit on message length as 
defined in SAE J1850 must be enforced by the user’s software. The number of bytes in a message 
(transmitted or received) has no meaning to the BDLC module.

— Step 1: Write the First Byte into the BDLC Data Register

To initiate a message transmission, the CPU simply loads the first byte of the message to be transmitted into the BDLC Data 
Register. The BDLC module will then perform the necessary bus acquisition duties to determine when the message transmission 
can begin.

Once the BDLC module determines that the SAE J1850 bus is free, a Start of Frame (SOF) symbol will be transmitted, followed 
by the byte written to the BDLC Data Register. Once the BDLC module readies this byte for transmission, the BDLC State Vector 
Register will reflect that the next byte can be written to the BDLC Data Register (TDRE interrupt).

If the user writes the first byte of a message to be transmitted to the BDLC Data Register and then 
determines that a different message should be transmitted, the user can write a new byte to the BDLC 
Data Register up until the transmission begins. This new byte will replace the original byte in the 
BDLC Data Register.

— Step 2: When TDRE is Indicated, Write the Next Byte into the BDLC Data Register

When a TDRE state is reflected in the BDLC State Vector Register, the CPU writes the next byte to be transmitted into the BDLC 
Data Register. This step is repeated until the last byte to be transmitted is written to the BDLC Data Register.

Due to the design and operation of the BDLC module, when transmitting a message the user may 
write two, or possibly even three of the bytes to be transmitted into the BDLC Data Register before 
the first RDRF interrupt occurs. For this reason, the user should never use receive interrupts to control 
the sequencing of bytes to be transmitted.

— Step 3: Write the Last Byte to the BDLC Data Register and Set TEOD

Once the user has written the last byte to be transmitted into the BDLC Data Register, the user then sets the TEOD bit in BDLC 
Control Register 2. When the TEOD bit is set, once the byte written to the BDLC Data Register is transmitted onto the bus, the 
BDLC module will begin transmitting the 8-bit CRC byte, as specified in SAE J1850. Following the CRC byte, the BDLC module 
will transmit an EOD symbol onto the SAE J1850 bus, indicating that this part of the message has been completed. If no IFR bytes 
are transmitted following the EOD, an EOF will be recognized and the message will be complete.

Setting the TEOD bit is the last step the CPU needs to take to complete the message transmission, and no further 
transmission-related interrupts will occur. Once the message has been completely received by the BDLC module, an EOF interrupt 
will be generated. However, this is technically a receive function which can be handled by the message reception routine.

While the TEOD bit is typically set immediately following the write of the last byte to the BDLC Data 
Register, it is also acceptable to wait until a TDRE interrupt is generated before setting the TEOD bit. 
While the example flowchart in 

 shows the TEOD bit being set after the write to the 

BDLC Data Register, either method is correct. If a TDRE interrupt is pending, it will be cleared when 
the TEOD bit is set.

While this is the basic transmit flow, at times the message transmit process will be interrupted. This can be due to a loss of arbitration to a 
higher priority message or due to an error being detected on the network. For the transmit routine, either of these events can be dealt with in 
a similar manner.

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Loss of Arbitration

If a loss of arbitration (LOA) occurs while the BDLC module is transmitting onto the SAE J1850 bus, the BDLC module will 
immediately stop transmitting, and a LOA status will be reflected in the BDLC State Vector Register. If the loss of arbitration has 
occurred on a byte boundary, an RDRF interrupt may also be pending once the LOA interrupt is cleared.

When a loss of arbitration occurs, the J1850 message handling software should immediately switch into the receive mode. If the 
TEOD bit was set, it will be cleared automatically. If another attempt is to be made to transmit the same message, the user must 
start the transmit sequence over from the beginning of the message.

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Error Detection