Freescale Semiconductor MPC5200B ユーザーズマニュアル

Freescale Semiconductor

20-47

This section includes sample flows for initializing the BDLC module and using it to transmit and receive messages.

To initialize the BDLC module, the user should first write the desired data to the configuration bits. The BDLC module should then be taken 
out of digital and analog loopback mode and enabled. Exiting from loopback mode will entail change of state indications in the BDLC State 
Vector Register which must be dealt with. Once this is complete, CPU interrupts can be enabled (if desired), and then the BDLC module is 
capable of SAE J1850 serial network communication. For an illustration of the sequence necessary for initializing the BDLC module, refer 
to 

Enter BDLC module Transmit

Routine

Write first message

byte to be transmitted

into DLCBDR

Is DLCBSVR = $00?

Yes

No

Load next byte to be

transmitted into DLCBDR

(clears TDRE)

Is DLCBSVR = $1C?

Yes

No

Is DLCBSVR = $14?

Yes

No

Is DLCBSVR = $10?

Yes

No

(TDRE)

(LOA)

(Invalid Symbol)

Attempt another

Yes

No

transmission?

Is this the last

Yes

No

byte?

Jump to BDLC module

Receive Routine

Once BDLC module detects

EOF, transmit

Set TEOD bit

in DLCBCR2

attempt is complete

Yes

No

IFR Received?

Jump to Receive IFR

Handling Routine

Exit BDLC module Transmit

Routine

Go to BDLC module

BREAK/Error Handling

Routine

For interrupt driven systems, 
this marks the beginning of the 
transmit section of the BDLC 
module interrupt service 
routine

NOTE: The EOF and CRC Error interrupts 
are handled in the BDLC module Receive 
Routine