Freescale Semiconductor MPC5200B ユーザーズマニュアル

Freescale Semiconductor

MPC5200B Users Guide, Rev. 1

Freescale Semiconductor

B-1

Appendix B
List of Registers

Section

CDM Registers ............................................................................................................................................5-11

CDM JTAG ID Number Register—MBAR + 0x0200 ......................................................................... 5-12

CDM Power On Reset Configuration Register—MBAR + 0x0204 .................................................... 5-12

CDM Bread Crumb Register—MBAR + 0x0208 ................................................................................ 5-14

CDM Configuration Register—MBAR + 0x020C............................................................................... 5-14

CDM 48MHz Fractional Divider Configuration Register—MBAR + 0x0210.................................... 5-15

CDM Clock Enable Register—MBAR + 0x0214 ................................................................................ 5-16

CDM System Oscillator Configuration Register—MBAR + 0x0218.................................................. 5-17

CDM Clock Control Sequencer Configuration Register—MBAR + 0x021C ..................................... 5-18

CDM Soft Reset Register—MBAR + 0x0220 ..................................................................................... 5-20

CDM System PLL Status Register—MBAR + 0x0224 ....................................................................... 5-20

PSC1 Mclock Config Register—MBAR + 0x0228 ............................................................................. 5-21

PSC2 Mclock Config Register—MBAR + 0x022C............................................................................. 5-22

PSC3 Mclock Config Register—MBAR + 0x0230 ............................................................................. 5-22

PSC6 (IrDA) Mclock Config Register—MBAR + 0x0234 ................................................................. 5-23

Section

Interrupt Controller Registers....................................................................................................................... 8-5

ICTL Peripheral Interrupt Mask Register—MBAR + 0x0500............................................................... 8-5

ICTL Peripheral Priority and HI/LO Select 1 Register —MBAR + 0x0504......................................... 8-7

ICTL Peripheral Priority and HI/LO Select 2 Register —MBAR + 0x0508......................................... 8-8

ICTL Peripheral Priority and HI/LO Select 3 Register —MBAR + 0x050C........................................ 8-8

ICTL External Enable and External Types Register —MBAR + 0x0510.............................................. 8-9

ICTL Critical Priority and Main Interrupt Mask Register—MBAR + 0x0514.................................... 8-10

ICTL Main Interrupt Priority and INT/SMI Select 1 Register —MBAR + 0x0518 ........................... 8-12

ICTL Main Interrupt Priority and INT/SMI Select 2 Register—MBAR + 0x051C............................ 8-13

ICTL Perstat, MainStat, MainStat, CritStat Encoded Register—MBAR + 0x0524............................. 8-14

ICTL Critical Interrupt Status All Register—MBAR + 0x0528 .......................................................... 8-15

ICTL Main Interrupt Status All Register—MBAR + 0x052C ............................................................. 8-16

ICTL Peripheral Interrupt Status All Register—MBAR + 0x0530...................................................... 8-17

ICTL Peripheral Interrupt Status All Register—MBAR + 0x0538...................................................... 8-18

ICTL Main Interrupt Emulation All Register—MBAR + 0x0540....................................................... 8-19

ICTL Peripheral Interrupt Emulation All Register—MBAR + 0x0544............................................... 8-20

ICTL IRQ Interrupt Emulation All Register—MBAR + 0x0548 ........................................................ 8-21

Section

GPIO Standard Registers—MBAR+0x0B00 ............................................................................................ 8-28

GPS Port Configuration Register—MBAR + 0x0B00......................................................................... 8-29

GPS Simple GPIO Enables Register—MBAR + 0x0B04.................................................................... 8-31

GPS Simple GPIO Open Drain Type Register —MBAR + 0x0B08.................................................... 8-33

GPS Simple GPIO Data Direction Register—MBAR + 0x0B0C........................................................ 8-34

GPS Simple GPIO Data Output Values Register —MBAR + 0x0B10 ................................................ 8-37

GPS Simple GPIO Data Input Values Register —MBAR + 0x0B14................................................... 8-38

GPS GPIO Output-Only Enables Register —MBAR + 0x0B18 ......................................................... 8-39

GPS GPIO Output-Only Data Value Out Register —MBAR + 0x0B1C............................................. 8-40

GPS GPIO Simple Interrupt Enable Register—MBAR + 0x0B20 ...................................................... 8-41

GPS GPIO Simple Interrupt Open-Drain Emulation Register —MBAR + 0x0B24............................ 8-42

GPS GPIO Simple Interrupt Data Direction Register —MBAR + 0x0B28......................................... 8-43

GPS GPIO Simple Interrupt Data Value Out Register —MBAR + 0x0B2C....................................... 8-43