Fujitsu D2529 ユーザーズマニュアル

D2529 (TX300 S4)

Technical Manual

13

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1 or 2 dual or quad core Intel

®

 Xeon™ processors 

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 2 processor sockets LGA771 for dual core Intel

®

 Xeon™ processors

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1x6, 2x6, 2x4 or 4 MB Second-Level-Cache (on-die unified, 64 byte cache-
line size)

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32 KB L1 Cache (on-die, data per core)

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32 KB L1 Cache (on-die, instruction per core)

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2 x 266 MHz or 333 MHz data bus (equals FSB 1066 or 1333: quadruple 
data rate (or quad pumping) delivers 4 bits of data per clock cycle) 

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2 VRM 11.0 onboard (EVRD)

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2 sots for memory riser cards with 8 PCI slots each

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FBD PC2-4200F or FDB PC2-5300F Fully Buffered DIMM memory modules 
with 512 MB, 1 Gbyte, 2 Gbyte and 4 Gbyte

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Maximum 64 Gbyte

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Minimum 1 Gbyte

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Maximum 4x8 Gbyte/s bandwidth

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Supports 4 FBD memory channels

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ECC multiple bit error detection and single bit error correction

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Memory scrubbing function

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Single Device Data Correction (SDDC) function (Chipkill™)

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Mirroring

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Sparing

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Intel

®

 Blackford chip set (Intel 5000P chipset)

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Single-channel Gigabit LAN controller (Broadcom 5708C)

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Super I/O controller (SMSC 47M107) 

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Flash EPROM for:
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local BIOS; flashable via bootable USB device, LAN or optional floppy 
disk

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SMSC8700 Fast Ethernet RMII Phy

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iRMC S2 with integrated VGA graphic controller