Fujitsu FR81S ユーザーズマニュアル
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
27
4.1.4.
FIFO BYTE Register: FBYTE
Function of this register changes for reading and writing.
For reading, FIFO byte register (FBYTE) shows valid data count of FIFO.
For writing, you will be able to configure whether to generate a reception interrupt when the reception FIFO
receives the specified number of data sets.
FBYTEn(n=0 to 11): Address Base addr + 22
H
(Access: Byte, Half-word,
Word)
15
14
13
12
11
10
9
8
bit
FBYTE2[7:0]
0
0
0
0
0
0
0
0
Initial value
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
Attribute
7
6
5
4
3
2
1
0
bit
FBYTE1[7:0]
0
0
0
0
0
0
0
0
Initial value
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
Attribute
[bit15 to bit8] FBYTE2 (FIFO Byte 2): FIFO2 data count display bits
[bit7 to bit0] FBYTE1 (FIFO Byte 1): FIFO1 data count display bits
[bit7 to bit0] FBYTE1 (FIFO Byte 1): FIFO1 data count display bits
The FBYTE register indicates valid data count written to or received at FIFO. The table below shows the
details of FCR1:FSEL bit settings.
FSEL
FIFO selection
Data count display
0
FIFO2: Reception FIFO, FIFO1:Transmission FIFO
FIFO2: FBYTE2, FIFO1: FBYTE1
1
FIFO2: Transmission FIFO, FIFO1: Reception FIFO
FIFO2: FBYTE2, FIFO1: FBYTE1
⋅
The initial value of FBYTE transfer count is 08
H
.
⋅
Set the data count at which you want to generate a reception interrupt flag with FBYTE for reception
FIFO. If the specified transfer count and data count display of FBYTE register match, the interrupt flag
(SSR:RDRF) will be set to "1".
⋅
In the case where all the conditions below are met, when reception idle continues for more than 8 baud
rate clocks, interrupt flag (SSR:RDRF) will be set to "1".
⋅
Reception FIFO idle detection enable bit (FCR1:FRIIE) is set to "1"
⋅
Data count contained in the reception FIFO does not reach the transfer count
⋅
If you read the RDR while the counter is counting 8 baud rate clocks, the counter will be reset to 0 and
start counting 8 clocks again. When reception FIFO is disabled, the counter will be reset to "0". When the
reception FIFO is enabled while any data is left in the reception FIFO, counting will be started once
again.
⋅
[CSIO] To receive data in the master operation mode (master reception), clear the SCR:TIE bit and
SCR:TBIE bit to "0", set the reception data count at the FBYTE register of transmission FIFO, and write
"0" to the FCR1:FDRQ bit. Then, it outputs serial clocks for the volume of data configured when the
SCR:TXE bit is "1", which allows you to receive the data volume you have configured. To set the
SCR:TIE bit and the SCR:TBIE bit to "1", set them to 1 after FCR1:FDRQ changes to "1".
⋅
[CSIO] When transmission data is written to TDR once, transmission FIFO’s FBYTE will be
incremented by +1. When SSR:AWC=0 and the data length is 20, 24, 32, a transmission data writing to
TDR must be separated to 2 times. The transmission FIFO’s FBYTE will be incremented by +2.
⋅
[CSIO] When reception data is read from RDR once, reception FIFO’s FBYTE will be decremented by
-1. When SSR:AWC=0 and the data length is 20, 24, 32, a reception data read from RDR must be
separated to 2 times. The reception FIFO’s FBYTE will be decremented by -2.
⋅
[I
2
C] To receive data in the master operation mode (master reception), clear the SMR:TIE bit to "0", set
the reception data count at FBYTE register of transmission FIFO, and write "0" to the FCR1:FDRQ bit.
It outputs the SCL clocks for the data volume configured. Then, the IBCR:INT bit will be set to "1". To
set the SMR:TIE bit to "1", set it to 1 after FCR1:FDRQ changes to "1".
MB91520 Series
MN705-00010-1v0-E
1340