Fujitsu FR81S ユーザーズマニュアル
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
73
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Transmission data is output in synchronization with a rising edge of the serial clock in the normal
transfer while it is output in synchronization with a falling edge of the serial clock in the SPI transfer.
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Reception data is sampled at a falling edge of the serial clock in the normal transfer while it is sampled at
a rising edge of the serial clock in the SPI transfer.
CS1SCINV
Serial chip select pin 1
Serial clock invert bit
0
Mark level "H" format
1
Mark level "L" format
Notes:
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This bit can be changed only when transmission and reception are disabled (SCR:TXE=RXE="0").
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In the slave mode (SCR:MS="0"), setting this bit has no effect.
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When data format of chip select is disabled (ESCR:CSFE="0"), setting this bit has no effect.
[bit5] CS1SPI: SPI support bit for chip select 1
If data format of chip select is enabled (ESCR:CSFE="1"), this bit is used to execute an SPI communication
when the serial chip select pin 1 is active.
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When this bit is set to "0": Normal synchronous communication.
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When this bit is set to "1": SPI communication supported.
CS1SPI
Serial chip select pin 1
SPI support bit
0
Normal synchronous transfer
1
SPI supported
Notes:
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This bit can be changed only when transmission and reception are disabled (SCR:TXE=RXE="0").
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In the slave mode (SCR:MS="0"), setting this bit has no effect.
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When data format of chip select is disabled (ESCR:CSFE="0"), setting this bit has no effect.
[bit4] CS1BDS: Transfer direction select bit for chip select 1
If data format of chip select is enabled (ESCR:CSFE="1"), this bit is used to select whether to transfer the
transfer serial data from the least significant bit (LSB first, BDS="0") or from the most significant bit (MSB
first, BDS="1") when the serial chip select pin 1 is active.
CS1BDS
Serial chip select pin 1
Transfer direction select bit
0
LSB first (transfer from the least significant bit)
1
MSB first (transfer from the most significant bit)
Notes:
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This bit can be changed only when transmission and reception are disabled (SCR:TXE=RXE="0").
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In the slave mode (SCR:MS="0"), setting this bit has no effect.
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When data format of chip select is disabled (ESCR:CSFE="0"), setting this bit has no effect.
[bit3 to bit0] CS1 L3, L2, L1, L0: Data length select bits for chip select 1
If data format of chip select is enabled (ESCR:CSFE="1"), these bits are used to specify the data length of
transmission/reception data when the serial chip select pin 1 is active.
MB91520 Series
MN705-00010-1v0-E
1386