Fujitsu FR81S ユーザーズマニュアル
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
6. Operation of CSIO
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
192
[1] Master operation (Set SCR:MS=0, SMR:SCKE=1, SCSCR:CSEN3-0="0000"b)
Transmission operation
(1) With serial data output enabled (SMR:SOE=1), transmission operation enabled (SCR:TXE=1), and
reception operation disabled (SCR:RXE=0), writing transmission data to TDR sets SSR:TDRE=0. This
resulted in outputting the transmission data in synchronization with a falling edge of the serial clock
(SCK) output.
(2) Outputting the transmission data in the first bit sets SSR:TDRE=1. When the transmission interrupt is
enabled (SCR:TIE=1), a transmission interrupt request will be generated. At this time, the transmission
data in the second byte can be written.
Reception operation
(1) With serial data output disabled (SMR:SOE=0), transmission operation enabled (SCR:TXE=1), and
reception operation enabled (SCR:RXE=1), writing dummy data to TDR samples the reception data at a
rising edge of the serial clock output (SCK).
(2) Receiving the last bit sets SSR:RDRF=1. When the reception interrupt is enabled (SCR:RIE=1), a
reception interrupt request will be generated. At this time, the receive data (RDR) can be read.
(3) Reading the receive data (RDR) clears SSR:RDRF to "0".
Notes:
⋅
If only reception operation is to be performed, write dummy data to TDR to output the serial clock
(SCK).
⋅
When transmission/reception FIFO is enabled, setting the FBYTE register to the number of frames to be
transferred outputs as many frames of serial clock (SCK) as the setting.
Transmission/Reception operation
(1) To perform transmission and reception at the same time, enable serial data output (SMR:SOE=1) and
enable transmission/reception operation (SCR:TXE, RXE=1).
(2) When transmission data is written in TDR, SSR:TDRE=0 is set, and the transmission data is output in
synchronization with the falling edge of serial clock (SCK) output. When transmission data of the first bit
is output, SSR:TDRE=1 is set, and when transmission interrupt is enabled (SCR:TIE=1), a transmission
interrupt request is output. At this time, the transmission data of the second byte can be written.
(3) Receive data is sampled by the rising edge of serial clock (SCK) output. When the last bit of receive data
is received, SSR:RDRF=1 is set. When reception interrupt is enabled (SCR:RIE=1), a reception interrupt
request is output. At this time, receive data (RDR) can be read. When receive data is read, SSR:RDRF is
cleared to "0".
MB91520 Series
MN705-00010-1v0-E
1505