Fujitsu FR81S ユーザーズマニュアル
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
7. Operation of LIN Interface (v2.1)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
278
Overview of pseudo framing error test mode
The pseudo framing error test can be executed on the side where the self-check on the side where data is
transmitted and data are received.
Figure 7-26 Outline of pseudo framing error test mode
SIN
SOUT
MPU
(header/response transmission node)
transceiver
Transmission
data
Reception data
(self-check)
Framing error
generation
transceiver
SIN
SOUT
MPU
(header/response reception node)
Reception data
Framing error
generation
Reversing
output of
Sync Field,
ID Field, data,
Stop bit of
checksum
It is necessary to set the framing error pseudo trouble setting bit to effective (LAMERT:FRET=1) by the
method of starting the pseudo error test mode to start the pseudo framing error test mode.
The start of the pseudo framing error test mode operates as follows.
⋅
Master
When Sync Field, ID Field, data, and checksum are transmitted, the value of the stop bit (" H" level) is
reversing output when the framing error pseudo trouble is set before the stop bit of each Field
(LAMERT:FRET=1).
The framing error occurs when receiving it, and "1" is set to flag bit (LAMESR: FRE).
⋅
Slave
When data and checksum are transmitted, the value of the stop bit ("H" level) is reversing output when the
framing error pseudo trouble is set before the stop bit of each Field (LAMERT:FRET=1).
When reception, the framing error occurs and "1" is set to flag bit (LAMESR: FRE).
The framing error is generation until the pseudo framing error test mode setting is released
(LAMESR:FRET=0).
Note:
The transmission/reception processing of the header/response part of the assist mode stops by framing error
detection (LAMESR:FRE=1).
MB91520 Series
MN705-00010-1v0-E
1591