Fujitsu FR81S ユーザーズマニュアル
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
8. Operation of I2C
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
340
Figure 8-10 Acknowledge (FIFO Disable, IBSR:RSA="0", and the Response Is NACK)
“L”by the INT bit Data
SCL
SDA R/W ACK
“0”writing
INT bit
RACK bit
FBT bit
TDRE bit
TDR register writing
Waiting to the address is as follows.
⋅
After receiving the acknowledge when the RSA bit is “0”
⋅
Before receiving the acknowledge when the RSA bit is “1”
It does not depend on the setting of WSEL.
Figure 8-11 Acknowledge (FIFO Disable, IBSR:RSA="0", and the Response Is NACK)
“L” by the INT bit
SCL
SDA R/W NACK
“0”write
INT bit
MSS bit
RACK bit
FBT bit
Stop condition
MB91520 Series
MN705-00010-1v0-E
1653