Fujitsu FR81S ユーザーズマニュアル
CHAPTER 3: CPU
10. Memory Protection Function (MPU)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CPU
FUJITSU SEMICONDUCTOR CONFIDENTIAL
48
10.4.3.
Data Access Protection Violation
The data access protection violation of the CPU is shown below.
The memory protection unit (MPU) monitors CPU data accesses and determines whether accesses (reads
and writes) to the corresponding area are permitted. If an access was not permitted, the MPU stores that
address and access information in the data access protection violation address register (DPVAR) and the
data access protection violation status register (DPVSR). However, if data access protection violation
information already exists in the above register (DPVSR.DPV =1), this is not overwritten. The data access
that caused the violation at this time is not performed.
If a data access protection violation occurs during the execution of an instruction that performs multiple
data accesses, the data accesses that had executed up until the violation occurred are not cancelled. If a data
access protection violation exception occurs during the LDM0, LDM1, STM0, STM1, FLDM, or FSTM
instructions, the list of remaining registers is stored in the exception status register ESR.RL.
If a data access protection violation occurs during the EIT processing sequence or the RETI instruction, the
CPU is halted and can only be recovered by break interrupt or reset.
MB91520 Series
MN705-00010-1v0-E
145