Fujitsu FR81S ユーザーズマニュアル
CHAPTER 47: ON CHIP DEBUGER (OCD)
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: ON CHIP DEBUGGER : OCD
FUJITSU SEMICONDUCTOR CONFIDENTIAL
20
5.1.2. Operating Mode Status Transition
Operating mode status transition is shown.
At INIT releasing (including RST accompanied by INIT), control transits to the debug state of the emulator
mode or to the free-run mode according to the mode command from DEBUG I/F in the chip reset sequence.
At RST releasing (not accompanied by INIT), control transits to the operating mode occurring before RST
generation. However, if a forced break request is issued after RST occurs in the user state, control transits to
the debug state of the emulator mode at RST releasing.
Moreover, transition between the free-run mode and user state of emulator mode is enabled by OCD register
control.
At transition from the reset status to the debug state, control first transits to the user state. In this case,
requesting a break by OCDU makes the following transition:
reset status → user state → (break) → debug state.
The transition conditions are shown below.
Figure 5-1 OCDU Operating Mode Transition Diagram
Reset state
B
A
A
D
E
C
Free-run mode
User state
Emulator mode
Break
Recovery
Debug state
[Transition indicated by broken lines]
Transition for when a reset (INIT, RST) occurs. All states transit to the reset state.
[Transition indicated by solid lines]
A: (1) Transition for when a mode command is received successfully in the DEBUG I/F chip reset sequence at INIT release after
the reset for which INIT is involved occurs.
(2) Transition after RST release after the resetfor which INIT is not involved occurs in the debug state.
(3) Transition at RST release when a forced break is requested before RST release after the reset without INIT occurs in the
user state or pseudo on-the-fly break is requested.
B: (1) Transition for when a mode command is not received successfully in the DEBUG I/F chip reset sequence at INIT release
after the reset for which INIT is involved occurs.
(2) Transition at RST release after the resetfor which INIT is not involved occurs in the free-run mode.
C: Transition at RST release after the resetfor which INIT is not involved occurs in the user state.
D: Transition for if "1" is written to the E_MSTSR:DMODE bit when OCDU operation is enabled in the free-run mode.
(INIT/RST)
E: Transition for if "0" is written to the E_MSTSR:DMODE bit in the user state
MB91520 Series
MN705-00010-1v0-E
2031