Fujitsu FR81S ユーザーズマニュアル
CHAPTER 7: RESET
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER :
RESET
FUJITSU SEMICONDUCTOR CONFIDENTIAL
10
4.2. Reset Control Register : RSTCR (ReSeT Control
Register)
The bit configuration of the reset control register is shown.
This register controls various types of reset issuance.
RSTCR : Address 0481
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
RDLY[2:0]
Reserved
SRST
Initial value
1
1
1
0
0
0
0
0
Attribute
R,W
R,W
R,W
R/W
R/W
R/W
R/W
R,W
[bit7 to bit5] RDLY[2:0] (Reset DeLaY) : Reset issue delay
These bits set the reset timeout value. A reset will be issued if all bus operations become idle or the timer has
counted to the reset timeout by this bit after a reset factor has been detected. (The latter is a case of irregular
reset). These bits can be written for only once after the reset.
RDLY[2:0]
Reset timeout value
000
PCLK × 2 cycles
001
PCLK × 4 cycles
010
PCLK × 8 cycles
011
PCLK × 16 cycles
100
PCLK × 32 cycles
101
PCLK × 64 cycles
110
PCLK × 128 cycles
111
PCLK × 256 cycles (Initial value)
[bit4 to bit1] Reserved
It writes, and both reading is not effective.
[bit0] SRST (Software ReSeT) : Software reset
You will be able to generate a software reset request by reading RSTCR after writing "1" to this bit.
After you have written "1" to this bit, any values written to RSTCR will be ignored until a reset is generated,
which means that register values cannot be changed.
In the RSTCR reading in the debugging state, reset is not generated.
SRST
Software reset
0
No output (initial value)
1
The set request is output by RSTCR reading.
MB91520 Series
MN705-00010-1v0-E
263