Fujitsu FR81S ユーザーズマニュアル
CHAPTER 8: DMA CONTROLLER (DMAC)
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : DMA CONTROLLER (DMAC)
FUJITSU SEMICONDUCTOR CONFIDENTIAL
18
When having allowed the abnormal completion interrupt (DCCRn:AIE), writing "0" to this bit clears the
interrupt. Writing "1" to this bit is ignored.
Make sure to clear this bit before enabling DMA operation. This bit will not be cleared automatically.
AC
Abnormal completion state
0
Abnormal completion undetected (initial value)
1
Abnormal completion
[bit1] SP (Stop) : Transfer suspension state by the transfer stop request
This bit indicates that a DMA transfer has been suspended by a transfer stop request from the transfer
request source. When having allowed the transfer suspension interrupt (DCCRn:SIE), writing "0" to this bit
clears the interrupt. Writing "1" to this bit is ignored.
Make sure to clear this bit before enabling DMA operation. This bit will not be cleared automatically.
SP
Transfer suspend state
0
Transfer suspend undetected (initial value)
1
Transfer suspend
[bit0] NC (Normal Completion) : Normal completion state
This bit indicates that DMA transfer has been completed successfully. After completing transfers as many
times as set by transfer count or when writing "1" to the corresponding channel's "DCCRn:CE" bit at the
time the transfer count is "0", the operation will complete normally. When having allowed the normal
completion interrupt (DCCRn:NIE), writing "0" to this bit clears the interrupt. Writing "1" to this bit is
ignored.
Make sure to clear this bit before enabling DMA operation. This bit will not be cleared automatically.
NC
Normal completion state
0
Normal completion undetected (initial value)
1
Normal completion
MB91520 Series
MN705-00010-1v0-E
317