Motorola CPCI-6020 ユーザーズマニュアル

XAD

[23:20]

Jumpers

1111

XCSR.GCSR.PUST
[3:0]

Generic Power Up Status Bits

(Software readable header)

XAD[19]

Resistor

0

State of bit can be 
inferred:

XCSR.CLAS 
(XCSR+$308)

Set PCI Configuration register CLAS to 
present class code for “bridge device”.

XAD[18]

Resistor

1

XCSR.PARB.ENA

Enable internal PCI arbiter

XAD[17]

Fixed

A=1

B=0

XCSR.XARB.ENA

Harrier A, enable internal PPC arbiter

Harrier B, disable internal PPC arbiter

XAD

[16:15]

Fixed

A=00

B=01

XCSR Register 
Group Base 
Address

Harrier A XCSR base addr. $FEFF0000

Harrier B XCSR base addr. $FEFF1000

XAD

[14-12]

On board 
logic sets 
ratio

000

XCSR.GCSR.RAT

Reserved

001

PPC-to-PCI clock ratio 3:2

010

PPC-to-PCI clock ratio 2:1

011

PPC-to-PCI clock ratio 5:2

100

PPC-to-PCI clock ratio 1:1

101

Reserved

110

PPC-to-PCI clock ratio 3:1

111

Reserved

XAD

[11:10]

Fixed

A=01

B=XX

XCSR.XPAT0.DW

Harrier A, Flash Bank A 16-bits wide

Harrier B, Flash Bank A not used.

XAD[9]

Jumper 
on board

A=1

B=0

XCSR.XPAT0.RVEN

Harrier A, Flash Bank A is Reset Vector.

Harrier B has no flash.

XAD

[8:7]

Resistor

A=01

B=xx

XCSR.XPAT1.DW

Harrier A, Flash Bank B to 16-bit width

Harrier B, Flash Bank B not used.

XAD[6]

Fixed

A=1

B=0

XCSR.XPAT1.RVEN

Harrier A, Flash Bank B is Reset Vector 
if and only if Bank A is not Reset Vector.

Harrier B has no flash.

XAD

[5:4]

Fixed

A=00

B=xx

XCSR.XPAT2.DW

Harrier A, Xport Ch. 2 8-bit width.

Harrier B, Xport Ch. 2 not used.

XAD[3]

Fixed

0

XCSR.XPAT2.RVEN

Disable Xport channel 2 as Reset Vector

XAD

[2:1]

Fixed

xx

XCSR.XPAT2.DW

Xport Channel 3 Data Width

Unused.

XAD[0]

Fixed

0

XCSR.XPAT3.RVEN

Disable Xport channel 3 as Reset Vector