Motorola MC68340 ユーザーズマニュアル

MOTOROLA

6- 21

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NOTE:
     1.  To cause another DMA transfer, DREQx is asserted after DACKx is asserted and before
          DACKx is negated.
     2.  DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle.

A31–A0

FC3–FC0

SIZ1–SIZ0

R/W

AS

DS

DSACKx

S0

S2

S4

S0

S4

S0

S2

S4

S0

S2

D15–D0

DREQx

DACKx

DONEx

(OUTPUT)

DMA READ

CPU CYCLE

CLKOUT

CPU CYCLE

DMA READ

If the fast termination option is used with external burst request mode (Figure 6-14), an
extra DMA cycle may result on every burst transfer. Normally, 

DREQ

≈

 is negated when

DACK

≈

 is returned. In the burst mode with fast termination selected, a new cycle starts

even if 

DREQ

≈

 is negated simultaneously with 

DACK

≈

 assertion.

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Freescale Semiconductor, Inc.

For More Information On This Product,

   Go to: www.freescale.com

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