Motorola MC68340 ユーザーズマニュアル
MOTOROLA
MC68340 USER’S MANUAL
3- 33
EXAMPLE B: A system uses error detection and correction on RAM contents. The
designer may:
designer may:
1. Delay
DSACK
≈
until data is verified and assert
BERR
and
HALT
simultaneously to
indicate to the MC68340 to automatically retry the error cycle (case 5), or if data is
valid, assert
valid, assert
DSACK
≈
(case 1).
2. Delay
DSACK
≈
until data is verified and assert
BERR
with or without
DSACK
≈
if
data is in error (case 3). This initiates exception processing for software handling of
the condition.
the condition.
3. Return
DSACK
≈
prior to data verification; if data is invalid,
BERR
is asserted on the
next clock cycle (case 4). This initiates exception processing for software handling of
the condition.
the condition.
4. Return
DSACK
≈
prior to data verification; if data is invalid, assert
BERR
and
HALT
on the next clock cycle (case 6). The memory controller can then correct the RAM
prior to or during the automatic retry.
prior to or during the automatic retry.
Table 3-4.
DSACK
≈
,
BERR
, and
HALT
Assertion Results
Asserted on Rising
Edge of State
Case
Num
Control
Signal
N
N + 2
Result
1
DSACK
≈
BERR
HALT
HALT
A
NA
NA
NA
S
NA
X
Normal cycle terminate and continue.
2
DSACK
≈
BERR
HALT
HALT
A
NA
A/S
S
NA
S
Normal cycle terminate and halt; continue
when
when
HALT
negated.
3
DSACK
≈
BERR
HALT
HALT
NA/A
A
NA
X
S
X
S
X
Terminate and take bus error exception,
possibly deferred.
possibly deferred.
4
DSACK
≈
BERR
HALT
HALT
A
NA
NA
NA
X
A
A
NA
Terminate and take bus error exception,
possibly deferred.
possibly deferred.
5
DSACK
≈
BERR
HALT
HALT
NA/A
A
A/S
X
S
S
S
S
Terminate and retry when
HALT
negated.
6
DSACK
≈
BERR
HALT
HALT
A
NA
NA
NA
X
A
A
A
A
Terminate and retry when
HALT
negated.
NOTES:
N — Number of the current even bus state (e.g., S2, S4, etc.)
A — Signal is asserted in this bus state
A — Signal is asserted in this bus state
NA — Signal is not asserted in this state
X — Don't care
S — Signal was asserted in previous state and remains asserted in this state
S — Signal was asserted in previous state and remains asserted in this state
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
..