Cypress EZ-USB FX2 PCB ユーザーズマニュアル

November 21, 2002

 Document No. 001-43117 Rev. ** 

 6 

AN1196

The solder stencil over the exposed paddle is required to per-
mit at least 50% solder application coverage. 

  is a

graph from Amkor research showing how solder void much
less than 50% has little influence on thermal transfer. The
package is a smaller one than the EZ-USB FX2 8-mm 56-
lead package, but the values do scale.

Figure 8.  Thermal Performance versus Solder Void

The manufacturing processes and practices of the assembly
operation govern the stencil pattern used. Generally, arrays
of either round or square patterns are used. A circular stencil
was used for one assembly run of boards.

Figure 9.  Stencil Area

 shows that the stencil area contains 25 holes. The

holes are 1 mm in diameter on a 1.25-mm pitch. The pad land
on the PCB is 6 mm square. This results in a solder coverage
of approximately 54 percent. A stencil could have fewer holes
but they would need to be larger and may not meet the mini-
mum 50% coverage requirement. A large pattern of four
squares could also be used. However, the larger the opening
of each hole or square the more likely solder sputtering or
out-gassing problems will occur. A solder stencil thickness of
0.125 mm is recommended for this package. 

 below

displays a cross-sectional area underneath the package. The
cross section is of only one via and is the recommended
dimensions for the via.

Figure 10.  Cross-section Area of via

Since there is no space under the package after soldering, it
is recommended to use a “No Clean,” type 3 solder paste.

Nitrogen purge is recommended during solder reflow.

Following the recommendations of this application note
should help the designer to produce a compliant and high-
performance USB 2.0 device design. Compliance can be
confirmed with testing at the often-scheduled USB-IF Compli-
ance Workshops. To the extent possible, developers of USB
products should test their designs for compliance prior to
attending one of the Workshops.