Cypress CY7C601xx ユーザーズマニュアル

Document 38-16016 Rev. *E

Page 24 of 68

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–

R/W

R/W

R/W

R/W

R/W

R/W

0

0

0

0

0

0

0

0

Bit [7:6]: Reserved
Bit 5: No Buzz
During sleep (the Sleep bit is set in the CPU_SCR Register—

), the LVD and POR detection circuit is turned on periodically 

to detect any POR and LVD events on the V

CC

 pin (the Sleep Duty Cycle bits in the ECO_TR are used to control the duty 

cycle—

). To facilitate the detection of POR and LVD events, the No Buzz bit is used to continuously enable the LVD and 

POR detection circuit during sleep. This results in a faster response to an LVD or POR event during sleep at the expense of a slightly 
higher than average sleep current. Obtaining the absolute lowest power usage in sleep mode requires the No Buzz bit be clear.
0 = The LVD and POR detection circuit is turned on periodically as configured in the Sleep Duty Cycle.
1 = The Sleep Duty Cycle value is overridden. The LVD and POR detection circuit is always enabled.
Note The periodic Sleep Duty Cycle enabling is independent with the sleep interval shown in the Sleep [1:0] bits below.
Bit [4:3]: Sleep Timer [1:0]

Note Sleep intervals are approximate.
Bit [2:0]: CPU Speed [2:0]
The enCoRe II LV operates over a range of CPU clock speeds. The reset value for the CPU Speed bits is zero; therefore, the default 
CPU speed is 3 MHz.

Note This register exists in the second bank of IO space. This requires setting the XIO bit in the CPU flags register.

Table 12-3.  OSC Control 0 (OSC_CR0) [0x1E0] [R/W]  (continued)

00

512 Hz

1.95 ms

6 ms

01

64 Hz

15.6 ms

47 ms

10

8 Hz

125 ms

375 ms

11

1 Hz

1 sec

3 sec

000 

3 MHz (Default)

Clock In/8

001

6 MHz

Clock In/4

010

12 MHz

Clock In/2

011

Reserved

Reserved

100

1.5 MHz

Clock In/16

101

750 KHz

Clock In/32

110

187 KHz

Clock In/128

111

Reserved

Reserved