Cypress CY7C601xx ユーザーズマニュアル
CY7C601xx, CY7C602xx
Document 38-16016 Rev. *E
Page 28 of 68
12.2.4 Internal Clock Trim
12.2.5 External Clock Trim
Table 12-6. IOSC Trim (IOSCTR) [0x34] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
foffset[2:0]
Gain[4:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
D
D
D
D
D
The IOSC Calibrate Register is used to calibrate the internal oscillator. The reset value is undefined, but during boot the SROM
writes a calibration value that is determined during manufacturing test. The ‘D’ indicates that the default value is trimmed to
24 MHz at 3.30V at power on.
Bit [7:5]: foffset [2:0]
This value is used to trim the frequency of the internal oscillator. These bits are not used in factory calibration and is zero. Setting
each of these bits causes the appropriate fine offset in oscillator frequency.
foffset bit 0 = 7.5 kHz
foffset bit 1 = 15 kHz
foffset bit 2 = 30 kHz
Bit [4:0]: Gain [4:0]
The effective frequency change of the offset input is controlled through the gain input. A lower value of the gain setting increases
the gain of the offset input. This value sets the size of each offset step for the internal oscillator. Nominal gain change
(KHz/offsetStep) at each bit, typical conditions (24 MHz operation):
Gain bit 0 = –1.5 kHz
Gain bit 1 = –3.0 kHz
Gain bit 2 = –6 kHz
Gain bit 3 = –12 kHz
Gain bit 4 = –24 kHz
writes a calibration value that is determined during manufacturing test. The ‘D’ indicates that the default value is trimmed to
24 MHz at 3.30V at power on.
Bit [7:5]: foffset [2:0]
This value is used to trim the frequency of the internal oscillator. These bits are not used in factory calibration and is zero. Setting
each of these bits causes the appropriate fine offset in oscillator frequency.
foffset bit 0 = 7.5 kHz
foffset bit 1 = 15 kHz
foffset bit 2 = 30 kHz
Bit [4:0]: Gain [4:0]
The effective frequency change of the offset input is controlled through the gain input. A lower value of the gain setting increases
the gain of the offset input. This value sets the size of each offset step for the internal oscillator. Nominal gain change
(KHz/offsetStep) at each bit, typical conditions (24 MHz operation):
Gain bit 0 = –1.5 kHz
Gain bit 1 = –3.0 kHz
Gain bit 2 = –6 kHz
Gain bit 3 = –12 kHz
Gain bit 4 = –24 kHz
Table 12-7. XOSC Trim (XOSCTR) [0x35] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
XOSC XGM [2:0]
Reserved
Mode
Read/Write
–
–
–
R/W
R/W
R/W
–
R/W
Default
0
0
0
D
D
D
–
D
This register is used to calibrate the external crystal oscillator. The reset value is undefined, but during boot the SROM writes a
calibration value that is determined during manufacturing test. This is the meaning of ‘D’ in the Default field.
Bit [7:5]: Reserved
Bit [4:2]: XOSC XGM [2:0]
Amplifier transconductance setting. The Xgm settings are recommended for resonators with frequencies of interest for the
enCoRe II LV as below:
calibration value that is determined during manufacturing test. This is the meaning of ‘D’ in the Default field.
Bit [7:5]: Reserved
Bit [4:2]: XOSC XGM [2:0]
Amplifier transconductance setting. The Xgm settings are recommended for resonators with frequencies of interest for the
enCoRe II LV as below:
Bit 1: Reserved
Bit 0: Mode
0 = Oscillator Mode
1 = Fixed Maximum Bias Test Mode
Bit 0: Mode
0 = Oscillator Mode
1 = Fixed Maximum Bias Test Mode
Resonator
XGM Setting
Worst Case R (Ohms)
6 MHz Crystal
001
403
12 MHz Crystal
011
201
Reserved
111
-
6 MHz Ceramic
001
70.4
12 MHz Ceramic
011
41