Cypress CY7C601xx ユーザーズマニュアル
CY7C601xx, CY7C602xx
Document 38-16016 Rev. *E
Page 45 of 68
17.1 SPI Data Register
When an interrupt occurs to indicate to firmware that a byte of receive data is available or the transmitter holding register is empty,
firmware has seven SPI clocks to manage the buffers—to empty the receiver buffer or to refill the transmit holding register. Failure to
meet this timing requirement results in incorrect data transfer.
firmware has seven SPI clocks to manage the buffers—to empty the receiver buffer or to refill the transmit holding register. Failure to
meet this timing requirement results in incorrect data transfer.
17.2 SPI Configure Register
Table 17-1. SPI Data Register (SPIDATA) [0x3C] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
SPIData[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
When read, this register returns the contents of the receive buffer. When written, it loads the transmit holding register.
Bit [7:0]: SPI Data [7:0]
Table 17-2. SPI Configure Register (SPICR) [0x3D] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Swap
LSB First
Comm Mode
CPOL
CPHA
SCLK Select
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit 7: Swap
0 = Swap function disabled
1 = The SPI block swaps its use of SMOSI and SMISO. Among other things, this is useful to implement single wire communi-
cations similar to SPI.
cations similar to SPI.
Bit 6: LSB First
0 = The SPI transmits and receives the MSB (Most Significant Bit) first.
1 = The SPI transmits and receives the LSB (Least Significant Bit) first.
Bit [5:4]: Comm Mode [1:0]
0 0: All SPI communication disabled
0 1: SPI master mode
1 0: SPI slave mode
1 1: Reserved
Bit 3: CPOL
This bit controls the SPI clock (SCLK) idle polarity.
0 = SCLK idles low
1 = SCLK idles high
Bit 2: CPHA
The Clock Phase bit controls the phase of the clock on which data is sampled.
shows the timing for various combi-
nations of LSB First, CPOL, and CPHA.
Bit [1:0]: SCLK Select
This field selects the speed of the master SCLK. When in master mode, SCLK is generated by dividing the base CPUCLK
Important Note for Comm Modes 01b or 10b (SPI Master or SPI Slave)
When configured for SPI, (SPI Use = 1 –
When configured for SPI, (SPI Use = 1 –
), the input and output direction of pins P1.3, P1.5, and P1.6 is set auto-
matically by the SPI logic. However, pin P1.4's input and output direction is NOT automatically set; it must be explicitly set by
firmware. For SPI Master mode, pin P1.4 is configured as an output; for SPI Slave mode, pin P1.4 is configured as an input.
firmware. For SPI Master mode, pin P1.4 is configured as an output; for SPI Slave mode, pin P1.4 is configured as an input.