Cypress CY7C601xx ユーザーズマニュアル
CY7C601xx, CY7C602xx
Document 38-16016 Rev. *E
Page 60 of 68
Figure 20-1. Clock Timing
20.2 AC Characteristics
Parameter
Description
Conditions
Min
Typical
Max
Unit
Clock
T
ECLKDC
External Clock Duty Cycle
45
55
%
T
ECLK2
External Clock Frequency
1
24
MHz
F
IMO
Internal Main Oscillator Frequency
With proper trim values loaded
[5]
18.72
26.4
MHz
F
ILO
Internal Low Power Oscillator
With proper trim values loaded
[5]
15.0001 50.0
KHz
GPIO Timing
T
R_GPIO
Output Rise Time
Measured between 10 and 90% Vdd
and Vreg with 50 pF load
and Vreg with 50 pF load
50
ns
T
F_GPIO
Output Fall Time
Measured between 10 and 90% Vdd
and Vreg with 50 pF load
and Vreg with 50 pF load
15
ns
SPI Timing
T
SMCK
SPI Master Clock Rate
F
CPUCLK
/6
2
MHz
T
SSCK
SPI Slave Clock Rate
2.2
MHz
T
SCKH
SPI Clock High Time
High for CPOL = 0, Low for CPOL = 1
125
ns
T
SCKL
SPI Clock Low Time
Low for CPOL = 0, High for CPOL = 1
125
ns
T
MDO
Master Data Output Time
SCK to data valid
–25
50
ns
T
MDO1
Master Data Output Time,
First bit with CPHA = 0
First bit with CPHA = 0
Time before leading SCK edge
100
ns
T
MSU
Master Input Data Setup time
50
ns
T
MHD
Master Input Data Hold time
50
ns
T
SSU
Slave Input Data Setup Time
50
ns
T
SHD
Slave Input Data Hold Time
50
ns
T
SDO
Slave Data Output Time
SCK to data valid
100
ns
T
SDO1
Slave Data Output Time,
First bit with CPHA = 0
First bit with CPHA = 0
Time after SS LOW to data valid
100
ns
T
SSS
Slave Select Setup Time
Before first SCK edge
150
ns
T
SSH
Slave Select Hold Time
After last SCK edge
150
ns
CLOCK
T
CYC
T
CL
T
CH