Nxp Semiconductors UM10237 ユーザーズマニュアル
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
104 of 792
NXP Semiconductors
UM10237
Chapter 6: LPC24XX Memory Accelerator Module (MAM)
7.
Register description
The MAM is controlled by the registers shown in
. More detailed descriptions
follow. Writes to any unused bits are ignored. A read of any unused bits will return a logic
zero.
zero.
[1]
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
7.1 MAM Control Register (MAMCR - 0xE01F C000)
Two configuration bits select the three MAM operating modes, as shown in
.
Following any reset, MAM functions are disabled. Software can turn memory access
acceleration on or off at any time allowing most of an application to be run at the highest
possible performance, while certain functions can be run at a somewhat slower but more
predictable rate if more precise timing is required.
acceleration on or off at any time allowing most of an application to be run at the highest
possible performance, while certain functions can be run at a somewhat slower but more
predictable rate if more precise timing is required.
Changing the MAM operating mode causes the MAM to invalidate all of the holding
latches, resulting in new reads of Flash information as required. This guarantees
synchronization of the MAM to CPU operation.
latches, resulting in new reads of Flash information as required. This guarantees
synchronization of the MAM to CPU operation.
7.2 MAM Timing Register (MAMTIM - 0xE01F C004)
The MAM Timing register determines how many CCLK cycles are used to access the
Flash memory. This allows tuning MAM timing to match the processor operating
frequency. Flash access times from 1 clock to 7 clocks are possible. Single clock Flash
accesses would essentially remove the MAM from timing calculations. In this case the
MAM mode may be selected to optimize power usage.
Flash memory. This allows tuning MAM timing to match the processor operating
frequency. Flash access times from 1 clock to 7 clocks are possible. Single clock Flash
accesses would essentially remove the MAM from timing calculations. In this case the
MAM mode may be selected to optimize power usage.
Table 98.
Summary of Memory Acceleration Module registers
Name
Description
Access Reset
value
Address
MAMCR
Memory Accelerator Module Control Register.
Determines the MAM functional mode, that is, to
what extent the MAM performance enhancements
are enabled. See
Determines the MAM functional mode, that is, to
what extent the MAM performance enhancements
are enabled. See
.
R/W
0x0
0xE01F C000
MAMTIM Memory Accelerator Module Timing control.
Determines the number of clocks used for Flash
memory fetches (1 to 7 processor clocks).
memory fetches (1 to 7 processor clocks).
R/W
0x07
0xE01F C004
Table 99.
MAM Control Register (MAMCR - address 0xE01F C000) bit description
Bit
Symbol
Value
Description
Reset
value
value
1:0
MAM_mode
_control
_control
These bits determine the operating mode of the MAM.
0
00
MAM functions disabled
01
MAM functions partially enabled
10
MAM functions fully enabled
11
Reserved. Not to be used in the application.
7:2
-
-
Unused, always 0.
0