Nxp Semiconductors UM10237 ユーザーズマニュアル

UM10237_2

© NXP B.V. 2008. All rights reserved.

– Memory traffic optimized by buffering and pre-fetching.

Enhanced Ethernet features:

– Receive filtering.

– Multicast and broadcast frame support for both transmit and receive.

– Optional automatic FCS insertion (CRC) for transmit.

– Selectable automatic transmit frame padding.

– Over-length frame support for both transmit and receive allows any length frames.

– Promiscuous receive mode.

– Automatic collision backoff and frame retransmission.

– Includes power management by clock switching.

– Wake-on-LAN power management support allows system wake-up: using the 

receive filters or a magic frame detection filter.

Physical interface:

– Attachment of external PHY chip through standard Media Independent Interface 

(MII) or standard Reduced MII (RMII) interface, software selectable.

– PHY register access is available via the Media Independent Interface Management 

(MIIM) interface.

 shows the internal architecture of the Ethernet block.

 

The block diagram for the Ethernet block consists of:

register

interface (AHB

slave)

DMA interface

(AHB master)

BU

S I

N

T

ER

F

AC

E

RECEIVE

DMA

TRANSMIT

DMA

RECEIVE

BUFFER

RECEIVE

FILTER

TRANSMIT

RETRY

TRANSMIT

FLOW

CONTROL

E

T

HE

RNE

T

 M

A

C

R

M

II A

D

A

P

T

E

R

MII or

RMII

MIIM

HOST

REGISTERS

AH

B BU

S

ETHERNET

BLOCK

MII

RMII

E

T

HE

RN

E

T

 P

HY

BU

S

IN

T

E

R

F

A

C

E