Nxp Semiconductors UM10237 ユーザーズマニュアル

UM10237_2

© NXP B.V. 2008. All rights reserved.

to a fragment of a frame. By using fragments, scatter/gather DMA can be done: transmit 
frames are gathered from multiple fragments in memory and receive frames can be 
scattered to multiple fragments in memory.

By stringing together fragments it is possible to create large frames from small memory 
areas. Another use of fragments is to be able to locate a frame header and frame payload 
in different places and to concatenate them without copy operations in the device driver.

For transmissions, the Last bit in the descriptor Control field indicates if the fragment is the 
last in a frame; for receive frames, the LastFrag bit in the StatusInfo field of the status 
words indicates if the fragment is the last in the frame. If the Last(Frag) bit is 0 the next 
descriptor belongs to the same Ethernet frame, If the Last(Frag) bit is 1 the next descriptor 
is a new Ethernet frame.

After reset, the Ethernet software driver needs to initialize the Ethernet block. During 
initialization the software needs to:

Remove the soft reset condition from the MAC

Configure the PHY via the MIIM interface of the MAC

Select RMII or MII mode

Configure the transmit and receive DMA engines, including the descriptor arrays

Configure the host registers (MAC1,MAC2 etc.) in the MAC

Enable the receive and transmit datapaths

Depending on the PHY, the software needs to initialize registers in the PHY via the MII 
Management interface. The software can read and write PHY registers by programming 
the MCFG, MCMD, MADR registers of the MAC. Write data should be written to the 
MWTD register; read data and status information can be read from the MRDD and MIND 
registers.

The Ethernet block supports RMII and MII PHYs. During initialization software must select 
MII or RMII mode by programming the Command register. After initialization, the RMII or 
MII mode should not be modified.

Before switching to RMII mode the default soft reset (MAC1 register bit 15) has to be 
deasserted when the Ethernet block is in MII mode . The phy_tx_clk and phy_rx_clk are 
necessary during this operation. In case an RMII PHY is used (which does not provide 
these clock signals), phy_tx_clk and phy_rx_clk can be connected to the phy_ref_clk.

Transmit and receive DMA engines should be initialized by the device driver by allocating 
the descriptor and status arrays in memory. Transmit and receive functions have their own 
dedicated descriptor and status arrays. The base addresses of these arrays need to be 
programmed in the TxDescriptor/TxStatus and RxDescriptor/RxStatus registers. The 
number of descriptors in an array matches the number of statuses in an array.

Please note that the transmit descriptors, receive descriptors and receive statuses are 8 
bytes each while the transmit statuses are 4 bytes each. All descriptor arrays and transmit 
statuses need to be aligned on 4 byte boundaries; receive status arrays need to be 
aligned on 8 byte boundaries. The number of descriptors in the descriptor arrays needs to