Nxp Semiconductors UM10237 ユーザーズマニュアル

UM10237_2

© NXP B.V. 2008. All rights reserved.

Each pair of nibbles transferred on the MII interface (or four pairs of bits for RMII) is 
transferred as a byte on the data write interface after being delayed by 128 or 136 cycles 
for filtering by the receive filter and buffer modules. The Ethernet block removes 
preamble, frame start delimiter, and CRC from the data and checks the CRC. To limit the 
buffer NoDescriptor error probability, three descriptors are buffered. The value of the 
RxProduceIndex is only updated after status information has been committed to memory, 
which is checked by an internal tag protocol in the memory interface. The software device 
driver will process the receive data, after which the device driver will update the 
RxConsumeIndex.

For an RMII PHY the data between the Ethernet block and the PHY is communicated at 
half the data-width and twice the clock frequency (50 MHz).

If a collision on the Ethernet occurs, it usually takes place during the collision window 
spanning the first 64 bytes of a frame. If collision is detected, the Ethernet block will retry 
the transmission. For this purpose, the first 64 bytes of a frame are buffered, so that this 
data can be used during the retry. A transmission retry within the first 64 bytes in a frame 
is fully transparent to the application and device driver software.

When a collision occurs outside of the 64 byte collision window, a LateCollision error is 
triggered, and the transmission is aborted. After a LateCollision error, the remaining data 
in the transmit frame will be discarded. The Ethernet block will set the Error and 
LateCollision bits in the frame’s status fields. The TxError bit in the IntStatus register will 
be set. If the corresponding bit in the IntEnable register is set, the TxError bit in the 
IntStatus register will be propagated to the CPU (via the Vectored Interrupt Controller). 
The device driver software should catch the interrupt and take appropriate actions.

The ‘RETRANSMISSION MAXIMUM’ field of the CLRT register can be used to configure 
the maximum number of retries before aborting the transmission.

For each received frame, the Ethernet block is able to detect the destination address and 
source address and from them calculate the corresponding hash CRCs. To perform the 
computation, the Ethernet block features two internal blocks: one is a controller 
synchronized with the beginning and the end of each frame, the second block is the CRC 
calculator.

When a new frame is detected, internal signaling notifies the controller.The controller 
starts counting the incoming bytes of the frame, which correspond to the destination 
address bytes. When the sixth (and last) byte is counted, the controller notifies the 
calculator to store the corresponding 32 bit CRC into a first inner register. Then the 
controller repeats counting the next incoming bytes, in order to get synchronized with the 
source address. When the last byte of the source address is encountered, the controller 
again notifies the CRC calculator, which freezes until the next new frame. When the 
calculator receives this second notification, it stores the present 32 bit CRC into a second 
inner register. Then the CRCs remain frozen in their own registers until new notifications 
arise.