Nxp Semiconductors UM10237 ユーザーズマニュアル

UM10237_2

© NXP B.V. 2008. All rights reserved.

 

The LCD controller is available on parts LPC2470 and LPC2478 only.

The LCD controller is configured using the following registers:

1. Power: In the PCONP register (

), set bit PCLCD.

Remark: The LCD is disabled on reset (PCLCD = 0).

 for power-up procedure.

2. Clock: see 

, and 

3. Pins: Enable the LCD controller port using the PINSEL11 register (

) and 

select individual LCD pins using PINSEL0 (

), PINSEL3 (

), 

), and PINSEL9 (

4. Configuration: see 

The LCD controller provides all of the necessary control signals to interface directly to a 
variety of color and monochrome LCD panels.

AHB bus master interface to access frame buffer.

Setup and control via a separate AHB slave interface.

Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.

Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays 
with 4 or 8-bit interfaces.

Supports single and dual-panel color STN displays.

Supports Thin Film Transistor (TFT) color displays.

Programmable display resolution including, but not limited to: 320x200, 320x240, 
640x200, 640x240, 640x480, 800x600, and 1024x768.

Hardware cursor support for single-panel displays.

15 gray-level monochrome, 3375 color STN, and 32K color palettized TFT support.

1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.

1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.

16 bpp true-color non-palettized, for color STN and TFT.

24 bpp true-color non-palettized, for color TFT.

Programmable timing for different display panels.