Nxp Semiconductors UM10237 ユーザーズマニュアル
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
303 of 792
NXP Semiconductors
UM10237
Chapter 12: LPC24XX LCD controller
[1]
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
7.1 LCD Configuration register (LCD_CFG, RW - 0xE01F C1B8)
The LCD_CFG register controls the prescaling of the clock used for LCD data generation.
The contents of the LCD_CFG register are described in
.
7.2 Horizontal Timing register (LCD_TIMH, RW - 0xFFE1 0000)
The LCD_TIMH register controls the Horizontal Synchronization pulse Width (HSW), the
Horizontal Front Porch (HFP) period, the Horizontal Back Porch (HBP) period, and the
Pixels-Per-Line (PPL).
Horizontal Front Porch (HFP) period, the Horizontal Back Porch (HBP) period, and the
Pixels-Per-Line (PPL).
The contents of the LCD_TIMH register are described in
0xFFE1 0C04
CRSR_CFG
Cursor Configuration register
0x0
R/W
0xFFE1 0C08
CRSR_PAL0
Cursor Palette register 0
0x0
R/W
0xFFE1 0C0C
CRSR_PAL1
Cursor Palette register 1
0x0
R/W
0xFFE1 0C10
CRSR_XY
Cursor XY Position register
0x0
R/W
0xFFE1 0C14
CRSR_CLIP
Cursor Clip Position register
0x0
R/W
0xFFE1 0C20
CRSR_INTMSK
Cursor Interrupt Mask register
0x0
R/W
0xFFE1 0C24
CRSR_INTCLR
Cursor Interrupt Clear register
0x0
WO
0xFFE1 0C28
CRSR_INTRAW
Cursor Raw Interrupt Status register
0x0
RO
0xFFE1 0C2C
CRSR_INTSTAT
Cursor Masked Interrupt Status register
0x0
RO
Table 259. Summary of LCD controller registers
…continued
Address
Name
Description
Reset
value
value
[1]
Access
Table 260. LCD Configuration register (LCD_CFG, RW - 0xE01F C1B8)
Bits
Function
Description
Reset
value
value
31:5
reserved
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The value read from a reserved bit is not defined.
-
4:0
CLKDIV
LCD panel clock prescaler selection.
The value in the this register plus 1 is used to divide the selected
input clock (see the CLKSEL bit in the LCD_POL register), to
produce the panel clock.
input clock (see the CLKSEL bit in the LCD_POL register), to
produce the panel clock.
0x0