Nxp Semiconductors UM10237 ユーザーズマニュアル

UM10237_2

© NXP B.V. 2008. All rights reserved.

The LCD_POL register controls various details of clock timing and signal polarity.

The contents of the LCD_POL register are described in 

.

 

23:16

VFP

Vertical front porch.

This is the number of inactive lines at the end of a frame, before 
the vertical synchronization period. The 8-bit VFP field specifies 
the number of line clocks to insert at the end of each frame. 
When a complete frame of pixels is transmitted to the LCD 
display, the value in VFP is used to count the number of line 
clock periods to wait.

After the count has elapsed, the vertical synchronization signal, 
LCDFP, is asserted in active mode, or extra line clocks are 
inserted as specified by the VSW bit-field in passive mode. VFP 
generates 0–255 line clock cycles. Program to zero on passive 
displays for improved contrast.

0x0

15:10

VSW

Vertical synchronization pulse width.

This is the number of horizontal synchronization lines. The 6-bit 
VSW field specifies the pulse width of the vertical 
synchronization pulse. Program the register with the number of 
lines required, minus one.

The number of horizontal synchronization lines must be small 
(for example, program to zero) for passive STN LCDs. The 
higher the value the worse the contrast on STN LCDs.

0x0

9:0

LPP

Lines per panel.

This is the number of active lines per screen. The LPP field 
specifies the total number of lines or rows on the LCD panel 
being controlled. LPP is a 10-bit value allowing between 1 and 
1024 lines. Program the register with the number of lines per 
LCD panel, minus 1. For dual panel displays, program the 
register with the number of lines on each of the upper and lower 
panels.

0x0

31:27

PCD_HI

Upper five bits of panel clock divisor.

See description for PCD_LO, in bits [4:0] of this register.

0x0

26

BCD

Bypass pixel clock divider.

Setting this to 1 bypasses the pixel clock divider logic. This is 
mainly used for TFT displays.

0x0

25:16

CPL

Clocks per line.

This field specifies the number of actual LCDDCLK clocks to the 
LCD panel on each line. This is the number of PPL divided by 
either 1 (for TFT), 4 or 8 (for monochrome passive), 2 2/3 (for 
color passive), minus one. This must be correctly programmed in 
addition to the PPL bit in the LCD_TIMH register for the LCD 
display to work correctly.

0x0