Nxp Semiconductors UM10237 ユーザーズマニュアル
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
309 of 792
NXP Semiconductors
UM10237
Chapter 12: LPC24XX LCD controller
7.6 Upper Panel Frame Base Address register (LCD_UPBASE, RW -
0xFFE1 0010)
The LCD_UPBASE register is the color LCD upper panel DMA base address register, and
is used to program the base address of the frame buffer for the upper panel. LCDUPBase
(and LCDLPBase for dual panels) must be initialized before enabling the LCD controller.
The base address must be doubleword aligned.
is used to program the base address of the frame buffer for the upper panel. LCDUPBase
(and LCDLPBase for dual panels) must be initialized before enabling the LCD controller.
The base address must be doubleword aligned.
Optionally, the value may be changed mid-frame to create double-buffered video displays.
These registers are copied to the corresponding current registers at each LCD vertical
synchronization. This event causes the LNBU bit and an optional interrupt to be
generated. The interrupt can be used to reprogram the base address when generating
double-buffered video.
These registers are copied to the corresponding current registers at each LCD vertical
synchronization. This event causes the LNBU bit and an optional interrupt to be
generated. The interrupt can be used to reprogram the base address when generating
double-buffered video.
The contents of the LCD_UPBASE register are described in
7.7 Lower Panel Frame Base Address register (LCD_LPBASE, RW -
0xFFE1 0014)
The LCD_LPBASE register is the color LCD lower panel DMA base address register, and
is used to program the base address of the frame buffer for the lower panel. LCDLPBase
must be initialized before enabling the LCD controller. The base address must be
doubleword aligned.
is used to program the base address of the frame buffer for the lower panel. LCDLPBase
must be initialized before enabling the LCD controller. The base address must be
doubleword aligned.
Table 264. Line End Control register (LCD_LE, RW - 0xFFE1 000C)
Bits
Function
Description
Reset
value
value
31:17
reserved
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The value read from a reserved bit is not defined.
-
16
LEE
LCD Line end enable.
0 = LCDLE disabled (held LOW).
1 = LCDLE signal active.
0x0
15:7
reserved
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The value read from a reserved bit is not defined.
-
6:0
LED
Line-end delay.
Controls Line-end signal delay from the rising-edge of the last
panel clock, LCDDCLK. Program with number of LCDCLK clock
periods minus 1.
panel clock, LCDDCLK. Program with number of LCDCLK clock
periods minus 1.
0x0
Table 265. Upper Panel Frame Base register (LCD_UPBASE, RW - 0xFFE1 0010)
Bits
Function
Description
Reset
value
value
31:3
LCDUPBASE
LCD upper panel base address.
This is the start address of the upper panel frame data in
memory and is doubleword aligned.
memory and is doubleword aligned.
0x0
2:0
reserved
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The value read from a reserved bit is not defined.
-