Nxp Semiconductors UM10237 ユーザーズマニュアル
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
313 of 792
NXP Semiconductors
UM10237
Chapter 12: LPC24XX LCD controller
7.10 Raw Interrupt Status register (LCD_INTRAW, RW - 0xFFE1 0020)
The LCD_INTRAW register contains status flags for various LCD controller events. These
flags can generate an interrupts if enabled by mask bits in the LCD_INTMSK register.
flags can generate an interrupts if enabled by mask bits in the LCD_INTMSK register.
The contents of LCD_INTRAW register are described in
.
2
LNBUIM
LCD next base address update interrupt enable.
0: The base address update interrupt is disabled.
1: Interrupt will be generated when the LCD base address
registers have been updated from the next address registers.
registers have been updated from the next address registers.
0x0
1
FUFIM
FIFO underflow interrupt enable.
0: The FIFO underflow interrupt is disabled.
1: Interrupt will be generated when the FIFO underflows.
0x0
0
reserved
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The value read from a reserved bit is not defined.
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Table 268. Interrupt Mask register (LCD_INTMSK, RW - 0xFFE1 001C)
Bits
Function
Description
Reset
value
value
Table 269. Raw Interrupt Status register (LCD_INTRAW, RW - 0xFFE1 0020)
Bits
Function
Description
Reset
value
value
31:5
reserved
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The value read from a reserved bit is not defined.
-
4
BERRAW
AHB master bus error raw interrupt status.
Set when the AHB master interface receives a bus error
response from a slave.
response from a slave.
Generates an interrupt if the BERIM bit in the LCD_INTMSK
register is set.
register is set.
0x0
3
VCompRIS
Vertical compare raw interrupt status.
Set when one of the four vertical regions is reached, as selected
by the LcdVComp bits in the LCD_CTRL register.
by the LcdVComp bits in the LCD_CTRL register.
Generates an interrupt if the VCompIM bit in the LCD_INTMSK
register is set.
register is set.
0x0
2
LNBURIS
LCD next address base update raw interrupt status.
Mode dependent. Set when the current base address registers
have been successfully updated by the next address registers.
Signifies that a new next address can be loaded if double
buffering is in use.
have been successfully updated by the next address registers.
Signifies that a new next address can be loaded if double
buffering is in use.
Generates an interrupt if the LNBUIM bit in the LCD_INTMSK
register is set.
register is set.
0x0
1
FUFRIS
FIFO underflow raw interrupt status.
Set when either the upper or lower DMA FIFOs have been read
accessed when empty causing an underflow condition to occur.
accessed when empty causing an underflow condition to occur.
Generates an interrupt if the FUFIM bit in the LCD_INTMSK
register is set.
register is set.
0
reserved
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The value read from a reserved bit is not defined.
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