Nxp Semiconductors UM10237 ユーザーズマニュアル
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
337 of 792
NXP Semiconductors
UM10237
Chapter 13: LPC24XX USB device controller
9.2 Clock control registers
9.2.1 USB Clock Control register (USBClkCtrl - 0xFFE0 CFF4)
This register controls the clocking of the USB Device Controller. Whenever software
wants to access the device controller registers, both DEV_CLK_EN and AHB_CLK_EN
must be set. The PORTSEL_CLK_EN bit need only be set when accessing the
USBPortSel register.
wants to access the device controller registers, both DEV_CLK_EN and AHB_CLK_EN
must be set. The PORTSEL_CLK_EN bit need only be set when accessing the
USBPortSel register.
The software does not have to repeat this exercise for every register access, provided that
the corresponding USBClkCtrl bits are already set. Note that this register is functional only
when the PCUSB bit of PCONP is set; when PCUSB is cleared, all clocks to the device
controller are disabled irrespective of the contents of this register. USBClkCtrl is a
read/write register.
the corresponding USBClkCtrl bits are already set. Note that this register is functional only
when the PCUSB bit of PCONP is set; when PCUSB is cleared, all clocks to the device
controller are disabled irrespective of the contents of this register. USBClkCtrl is a
read/write register.
9.2.2 USB Clock Status register (USBClkSt - 0xFFE0 CFF8)
This register holds the clock availability status. The bits of this register are ORed together
to form the USB_NEED_CLK signal. When enabling a clock via USBClkCtrl, software
should poll the corresponding bit in USBClkSt. If it is set, then software can go ahead with
the register access. Software does not have to repeat this exercise for every access,
provided that the USBClkCtrl bits are not disturbed. USBClkSt is a read only register.
to form the USB_NEED_CLK signal. When enabling a clock via USBClkCtrl, software
should poll the corresponding bit in USBClkSt. If it is set, then software can go ahead with
the register access. Software does not have to repeat this exercise for every access,
provided that the USBClkCtrl bits are not disturbed. USBClkSt is a read only register.
Table 294. USB Port Select register (USBPortSel - address 0xFFE0 C110) bit description
Bit
Symbol
Value
Description
Reset value
1:0
PORTSEL
0x0
The USB device controller signals are mapped to
the U1 port: USB_CONNECT1, USB_UP_LED1,
USB_D+1, USB_D
the U1 port: USB_CONNECT1, USB_UP_LED1,
USB_D+1, USB_D
−1.
0
0x3
The USB device controller signals are mapped to
the U2 port:USB_CONNECT2, USB_UP_LED2,
USB_D+2, USB_D
the U2 port:USB_CONNECT2, USB_UP_LED2,
USB_D+2, USB_D
−2
31:2
-
-
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is
not defined.
reserved bits. The value read from a reserved bit is
not defined.
NA
Table 295. USBClkCtrl register (USBClkCtrl - address 0xFFE0 CFF4) bit description
Bit
Symbol
Description
Reset
value
value
0
-
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is
not defined.
reserved bits. The value read from a reserved bit is
not defined.
NA
1
DEV_CLK_EN
Device clock enable. Enables the usbclk input to the
device controller
device controller
0
2
-
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is
not defined.
reserved bits. The value read from a reserved bit is
not defined.
NA
3
PORTSEL_CLK_EN
Port select register clock enable.
NA
4
AHB_CLK_EN
AHB clock enable
0
31:5
-
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is
not defined.
reserved bits. The value read from a reserved bit is
not defined.
NA