Nxp Semiconductors UM10237 ユーザーズマニュアル

UM10237_2

© NXP B.V. 2008. All rights reserved.

The dev_dma_need_clk signal is asserted on any Device controller DMA access to 
memory. Once asserted, it remains active for 2 ms (2 frames), to help assure that DMA 
throughput is not affected by any latency associated with re-enabling ahb_master_clk. 
2 ms after the last DMA access, dev_dma_need_clk is de-asserted to help conserve 
power. This signal allows AHB_CLK_EN to be cleared during normal operation.

The Host controller has two clock request signals, host_need_clk and 
host_dma_need_clk. When asserted, these signals turn on the host’s 48 MHz clock and 
ahb_master_clk respectively.

The host_need_clk signal is asserted while the Host controller functional state is not 
UsbSuspend, or if the functional state is UsbSuspend and resume signaling or a 
disconnect is detected on the USB bus. This signal allows HOST_CLK_EN to be cleared 
during normal operation when software does not need to access the Host controller 
registers – the Host will continue to function normally and automatically shut off its clock 
when it goes into the UsbSuspend state.

The host_dma_need_clk signal is asserted on any Host controller DMA access to 
memory. Once asserted, it remains active for 2 ms (2 frames), to help assure that DMA 
throughput is not affected by any latency associated with re-enabling ahb_master_clk. 
2 ms after the last DMA access, host_dma_need_clk is de-asserted to help conserve 
power. This signal allows AHB_CLK_EN to be cleared during normal operation.

The LPC2400 can be configured to wake up from Power Down mode on any USB bus 
activity. When the USBWAKE bit is set in the INTWAKE register, the assertion of the 
USB_NEED_CLK signal causes the chip to wake up from Power Down.

Before Power Down mode can be entered when USBWAKE is set, USB_NEED_CLK 
must be de-asserted. This is accomplished by clearing all of the CLK_EN bits in 
OTGClkCtrl and putting the Host controller into the UsbSuspend functional state. If it is 
necessary to wait for either of the dma_need_clk signals or the dev_need_clk to be 
de-asserted, the status of USB_NEED_CLK can be polled in the USBIntSt register to 
determine when they have all been de-asserted.

The LPC2400 OTG device controller initialization includes the following steps:

1. Enable the device controller by setting the PCUSB bit of PCONP.

2. Configure and enable the PLL and Clock Dividers to provide 48 MHz for usbclk, and 

the desired frequency for cclk. For correct operation of synchronization logic in the 
device controller, the minimum cclk frequency is 18 MHz. For the procedure for 
determining the PLL setting and configuration, see 

.

3. Enable the desired controller clocks by setting their respective CLK_EN bits in the 

USBClkCtrl register. Poll the corresponding CLK_ON bits in the USBClkSt register 
until they are set.