Nxp Semiconductors UM10237 ユーザーズマニュアル
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
437 of 792
NXP Semiconductors
UM10237
Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter
4.12 UARTn Fractional Divider Register (U0FDR - 0xE000 C028, U2FDR -
0xE007 8028, U3FDR - 0xE007 C028)
The UART0/2/3 Fractional Divider Register (U0/2/3FDR) controls the clock pre-scaler for
the baud rate generation and can be read and written at the user’s discretion. This
pre-scaler takes the APB clock and generates an output clock according to the specified
fractional requirements.
the baud rate generation and can be read and written at the user’s discretion. This
pre-scaler takes the APB clock and generates an output clock according to the specified
fractional requirements.
Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of
the DLL register must be 3 or greater.
the DLL register must be 3 or greater.
This register controls the clock pre-scaler for the baud rate generation. The reset value of
the register keeps the fractional capabilities of UART0/2/3 disabled making sure that
UART0/2/3 is fully software and hardware compatible with UARTs not equipped with this
feature.
the register keeps the fractional capabilities of UART0/2/3 disabled making sure that
UART0/2/3 is fully software and hardware compatible with UARTs not equipped with this
feature.
UART0/2/3 baudrate can be calculated as (n = 0/2/3):
(2)
Where PCLK is the peripheral clock, U0/2/3DLM and U0/2/3DLL are the standard
UART0/2/3 baud rate divider registers, and DIVADDVAL and MULVAL are UART0/2/3
fractional baudrate generator specific parameters.
UART0/2/3 baud rate divider registers, and DIVADDVAL and MULVAL are UART0/2/3
fractional baudrate generator specific parameters.
1
2
8
× T
PCLK
1
3
16
× T
PCLK
1
4
32
× T
PCLK
1
5
64
× T
PCLK
1
6
128
× T
PCLK
1
7
256
× T
PCLK
Table 391: IrDA Pulse Width
FixPulseEn
PulseDiv
IrDA Transmitter Pulse width (µs)
Table 392: UARTn Fractional Divider Register (U0FDR - address 0xE000 C028,
U2FDR - 0xE007 8028, U3FDR - 0xE007 C028) bit description
Bit
Function
Value Description
Reset
value
value
3:0
DIVADDVAL
0
Baud-rate generation pre-scaler divisor value. If this field is
0, fractional baud-rate generator will not impact the UARTn
baudrate.
0, fractional baud-rate generator will not impact the UARTn
baudrate.
0
7:4
MULVAL
1
Baud-rate pre-scaler multiplier value. This field must be
greater or equal 1 for UARTn to operate properly,
regardless of whether the fractional baud-rate generator is
used or not.
greater or equal 1 for UARTn to operate properly,
regardless of whether the fractional baud-rate generator is
used or not.
1
31:8
-
NA
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
bits. The value read from a reserved bit is not defined.
0
UARTn
baudrate
PCLK
16
256
UnDLM
×
UnDLL
+
(
)
×
1
DivAddVal
MulVal
-----------------------------
+
⎝
⎠
⎛
⎞
×
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