Nxp Semiconductors UM10237 ユーザーズマニュアル
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
45 of 792
NXP Semiconductors
UM10237
Chapter 4: LPC24XX Clocking and power control
register) so that software can determine when the oscillator is running and stable. At that
point, software can control switching to the main oscillator as a clock source. Prior to
starting the main oscillator, a frequency range must be selected by configuring the
OSCRANGE bit in the SCS register.
point, software can control switching to the main oscillator as a clock source. Prior to
starting the main oscillator, a frequency range must be selected by configuring the
OSCRANGE bit in the SCS register.
2.3 RTC oscillator
The RTC oscillator can be used as the clock source for the RTC, and/or the watchdog
timer. Also, the RTC oscillator can be used to drive the PLL and the CPU.
timer. Also, the RTC oscillator can be used to drive the PLL and the CPU.
3.
Register description
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
appear in the description of each function.
[1]
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
3.1 Clock source selection multiplexer
Several clock sources may be chosen to drive the PLL and ultimately the CPU and
on-chip peripheral devices. The clock sources available are the main oscillator, the RTC
oscillator, and the Internal RC (IRC) oscillator.
on-chip peripheral devices. The clock sources available are the main oscillator, the RTC
oscillator, and the Internal RC (IRC) oscillator.
The clock source selection can only be changed safely when the PLL is not connected.
For a detailed description of how to change the clock source in a system using the PLL
see
For a detailed description of how to change the clock source in a system using the PLL
see
.
Note the following restrictions regarding the choice of clock sources:
Table 41.
Summary of system control registers
Name
Description
Access
Reset
value
value
Address
Clock source selection
CLKSRCSEL
Clock Source Select Register
R/W
0
0xE01F C10C
Phase Locked Loop
PLLCON
PLL Control Register
R/W
0
0xE01F C080
PLLCFG
PLL Configuration Register
R/W
0
0xE01F C084
PLLSTAT
PLL Status Register
RO
0
0xE01F C088
PLLFEED
PLL Feed Register
WO
NA
0xE01F C08C
Clock dividers
CCLKCFG
CPU Clock Configuration Register
R/W
0
0xE01F C104
USBCLKCFG
USB Clock Configuration Register
R/W
0
0xE01F C108
IRCTRIM
IRC Trim Register
R/W
0xA0
0xE01F C1A4
PCLKSEL0
Peripheral Clock Selection register 0.
R/W
0
0xE01F C1A8
PCLKSEL1
Peripheral Clock Selection register 1.
R/W
0
0xE01F C1AC
Power control
PCON
Power Control Register
R/W
0
0xE01F C0C0
INTWAKE
Interrupt Wakeup Register
R/W
0
0xE01F C144
PCONP
Power Control for Peripherals Register
R/W
0x03BE
0xE01F C0C4