Nxp Semiconductors UM10237 ユーザーズマニュアル
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
457 of 792
NXP Semiconductors
UM10237
Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter
4.11 UART1 Modem Status Register (U1MSR - 0xE001 0018)
The U1MSR is a read-only register that provides status information on the modem input
signals. U1MSR[3:0] is cleared on U1MSR read. Note that modem signals have no direct
affect on UART1 operation, they facilitate software implementation of modem signal
operations.
signals. U1MSR[3:0] is cleared on U1MSR read. Note that modem signals have no direct
affect on UART1 operation, they facilitate software implementation of modem signal
operations.
5
Transmitte
r Holding
Register
Empty
(THRE)
r Holding
Register
Empty
(THRE)
0
THRE is set immediately upon detection of an empty UART1
THR and is cleared on a U1THR write.
THR and is cleared on a U1THR write.
1
U1THR contains valid data.
1
U1THR is empty.
6
Transmitte
r Empty
(TEMT)
r Empty
(TEMT)
0
TEMT is set when both U1THR and U1TSR are empty; TEMT is
cleared when either the U1TSR or the U1THR contain valid data.
cleared when either the U1TSR or the U1THR contain valid data.
1
U1THR and/or the U1TSR contains valid data.
1
U1THR and the U1TSR are empty.
7
Error in RX
FIFO
(RXFE)
FIFO
(RXFE)
0
U1LSR[7] is set when a character with a RX error such as framing
error, parity error or break interrupt, is loaded into the U1RBR.
This bit is cleared when the U1LSR register is read and there are
no subsequent errors in the UART1 FIFO.
error, parity error or break interrupt, is loaded into the U1RBR.
This bit is cleared when the U1LSR register is read and there are
no subsequent errors in the UART1 FIFO.
0
U1RBR contains no UART1 RX errors or U1FCR[0]=0.
1
UART1 RBR contains at least one UART1 RX error.
Table 408: UART1 Line Status Register (U1LSR - address 0xE001 0014, Read Only) bit
description
Bit Symbol
Value Description
Reset
Value
Value
Table 409: UART1 Modem Status Register (U1MSR - address 0xE001 0018) bit description
Bit Symbol Value Description
Reset
Value
Value
0
Delta
CTS
CTS
0
Set upon state change of input CTS. Cleared on an U1MSR read.
0
No change detected on modem input, CTS.
1
State change detected on modem input, CTS.
1
Delta
DSR
DSR
0
Set upon state change of input DSR. Cleared on an U1MSR read.
0
No change detected on modem input, DSR.
1
State change detected on modem input, DSR.
2
Trailing
Edge RI
Edge RI
0
Set upon low to high transition of input RI. Cleared on an U1MSR
read.
read.
0
No change detected on modem input, RI.
1
Low-to-high transition detected on RI.
3
Delta
DCD
DCD
0
Set upon state change of input DCD. Cleared on an U1MSR read.
0
No change detected on modem input, DCD.
1
State change detected on modem input, DCD.
4
CTS
Clear To Send State. Complement of input signal CTS. This bit is
connected to U1MCR[1] in modem loopback mode.
connected to U1MCR[1] in modem loopback mode.
0