Nxp Semiconductors UM10237 ユーザーズマニュアル
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
471 of 792
NXP Semiconductors
UM10237
Chapter 18: LPC24XX CAN controllers CAN1/2
6.5 Error Management Logic (EML)
The EML is responsible for the error confinement. It gets error announcements from the
BSP and then informs the BSP and IML about error statistics.
BSP and then informs the BSP and IML about error statistics.
6.6 Bit Timing Logic (BTL)
The Bit Timing Logic monitors the serial CAN Bus line and handles the Bus line related bit
timing. It synchronizes to the bit stream on the CAN Bus on a "recessive" to "dominant"
Bus line transition at the beginning of a message (hard synchronization) and
re-synchronizes on further transitions during the reception of a message (soft
synchronization). The BTL also provides programmable time segments to compensate for
the propagation delay times and phase shifts (e.g. due to oscillator drifts) and to define the
sample point and the number of samples to be taken within a bit time.
timing. It synchronizes to the bit stream on the CAN Bus on a "recessive" to "dominant"
Bus line transition at the beginning of a message (hard synchronization) and
re-synchronizes on further transitions during the reception of a message (soft
synchronization). The BTL also provides programmable time segments to compensate for
the propagation delay times and phase shifts (e.g. due to oscillator drifts) and to define the
sample point and the number of samples to be taken within a bit time.
6.7 Bit Stream Processor (BSP)
The Bit Stream Processor is a sequencer, controlling the data stream between the
Transmit Buffer, Receive Buffers and the CAN Bus. It also performs the error detection,
arbitration, stuffing and error handling on the CAN Bus.
Transmit Buffer, Receive Buffers and the CAN Bus. It also performs the error detection,
arbitration, stuffing and error handling on the CAN Bus.
6.8 CAN controller self-tests
The CAN controller of the LPC2000 family supports two different options for self-tests:
•
Global Self-Test (setting the self reception request bit in normal Operating Mode)
•
Local Self-Test (setting the self reception request bit in Self Test Mode)
Fig 75. Receive buffer layout for standard and extended frame format configurations
RX
Frame info
unused
ID Index
ID.28 ... ID.18
RX Data 4
RX Data 3
RX Data 2
RX Data 1
RX Data 8
RX Data 7
RX Data 6
RX Data 5
unused
31
24 23
16 15
10 9 8 7
0
RFS
RID
RDA
RDB
Descriptor
Field
Data Field
Standard Frame Format (11-bit Identifier)
Frame info
unused
RX DLC
ID.28 ... ID.00
RX Data 4
RX Data 3
RX Data 2
RX Data 1
RX Data 8
RX Data 7
RX Data 6
RX Data 5
31
24 23
16 15
RFS
RID
RDA
RDB
Descriptor
Field
Data Field
Extended Frame Format (29-bit Identifier)
RX DLC
RX
unused
unused
ID Index
unused
10 9 8 7
0
BPM=bypass
message